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Recently, researchers are targeting low-power consumption, and integrating more blocks on-chip. This paper proposes a 1GS/s 6-bit time-based analog-to-digital converter (T-ADC) for front-end receivers. This T-ADC eliminates the preprocessing analog blocks, and reduces power consumption by removing the power-hungry sample and hold circuit. A prototype of the proposed T-ADC is implemented in 65nm CMOS...
In conventional design of Nauta transconductor, the limitation of output voltage swing is usually the price for very high DC-gain due to inevitable non-linear effects in the transconductor. Nevertheless, a new design of Nauta transconductor in sub-micron CMOS technology with digitally-controlled transconductance may bring along opportunities to adjust the intrinsic gain of Nauta transconductor which,...
This paper presents a seven level inverter utilizing switched-capacitor technique. Proposed topology employs two asymmetric DC voltage sources as input and generates a multilevel staircase output. The structure includes a front-end switched-capacitor based DC-DC converter cascaded by a back-end H-bridge inverter. The frontend SC DC-DC converter feeds three DC voltage levels to the H-bridge inverter...
Static Random Access memory (SRAM) has a dense and regular layout structure with Bitlines (BL) and complementary Bitlines (BLN) running simultaneously along with power and ground lines. It can result in fabrication failures during wafer processing. Memory test algorithms read and write specific data in particular sequence so that maximum possible functional failures could be detected during testing...
Flash converters have high speed conversion rate compared to other types of Analog to digital converter (ADC). As precision increases, Flash ADC requires large number of comparators compared to other ADCs. Hence, the increase in chip area, power consumption and cost of Flash converters makes trade off for many applications. So, the low power Flash ADC is aimed to be designed with less number of low...
The paper deals with very accurate and effective simulation of Complementary Metal-Oxide-Semiconductor (CMOS) transistors which are used to construct basic logic gates (inverter, NAND and NOR) and their composites (XOR, AND, OR). The transistors are substituted by a resistor-capacitor (RC) circuit and the circuit is described by a system of differential algebraic equations (DAEs). These equations...
This paper, proposed a hybrid full adder with low power and less area using 8 transistors. Majority not gate and GDI techniques are collectively used for design this hybrid full adder. Some beforehand composed cells endure from non-full swing output, low speed, and high power utilization issues. While the new full adder has insignificant range overhead, it has enhanced the power Utilization of the...
Memristors are emerging devices known by their nonvolability, compatibility with CMOS processes and high density in circuits density in circuits mostly owing to the crossbar nanoarchitecture. One of their most notable applications is in the memory system field. Despite their promising characteristics and the advancements in this emerging technology, variability and reliability are still principal...
This paper introduces a single-stage isolated 48V-to-1.8V point-of-load converter based on the impedance control network (ICN) resonant converter architecture. This point-of-load ICN converter achieves large step-down while maintaining high efficiency across a wide range of input voltage and output power. Large step-down is achieved using a novel immittance network transformer and a resonant current-doubler...
We optimize and compare the performance of synchronous and asynchronous comparators across near-threshold and nominal supply voltage (0.5∼1V). Comparators are the key components that determine the fundamental performance of analog-to-digital conversion in control and digital-signal processing (DSP) systems. While the asynchronous comparator has been considered inferior, operation of transistors in...
Design and simulation problems of high power full-bridge boost converter with 175…320 VDC supply voltage are considered. The converter under investigation consists of a full-bridge inverter, a boost high-frequency transformer, a diode rectifier connected to a capacitive filter and an active load. Additional inductance, connected in series with the transformers primary winding, is brought in the converters...
On paper, Gallium nitride (GaN) transistor promises exceptional performance when used in converters operating at high switching frequency; nonetheless, reduction in their performance when used in real circuits have been observed. Previous experiments show that tested GaN transistors can display excessive loss of up to three times their predicted values under certain test conditions. This paper evaluates...
The Internet of Things (IoT) is currently a main focus of research across disciplines. In a household IoT environment, almost all devices are connected to the internet. In the case of a smart city, most of the city homes and departments are managed through the network. One small security vulnerability is enough to take down an entire city or parts of it. Hence communications should be encrypted. Physical...
This paper presents a highly power efficient amplifier. By stacking inverters and splitting the capacitor feedback network, the proposed amplifier achieves 6-time current reuse, thereby significantly boosting gm and lowering noise but without increasing power. A novel biasing scheme is devised to ensure robust operation under 1V supply. A prototype in 180nm CMOS has 5.5uV rms noise within 10kHz BW...
In this study, a mode transition scheme between a single phase half bridge 2-level voltage source converter (VSC) and a 3-level T-type VSC is proposed. The efficiency of 3-level T-type VSC can be increased by the mode transition scheme. The mode transition scheme select the efficient operation method between a 2-level and 3-level VSC. The 2-level VSC or 3-level VSC operation method are selected depending...
In this paper we examine a new architecture for the inverter used in the conversion of electric energy produced from sources of renewable energy. This type of inverter is particular because the compensation of current with double frequency is performed by a special block. In this block, like in the inverter, the switching of electronic keys is realized using the Triangular Current Mode method, which...
Logical elements for translation lookaside buffers were designed with single-event compensations and simulated on the bulk 65-nm CMOS design rule. The effects of upsets and single-event transients under impacts of single nuclear particles on MOS logical elements were minimized by the hardening the design. The basis of the fault-tolerant design is the hardened main row elements of the common matrix...
In this paper an analytic model of the inverter static noise margin (SNM) is presented. The drain-induced barrier lowering (DIBL) effects are considered in view of the fact that their influence becomes more critical in nanometer (below 90 nm) bulk CMOS nodes, as devices are dimensioned with minimum sizes and operate in sub-threshold region. The inclusion of body bias effect in the SNM model is proposed...
We present the design of a low-power 4-bit 1GS/s folding-flash ADC with a folding factor of two in standard 65nm CMOS technology. The design of a new unbalanced double-tail dynamic comparator affords an ultra-low power operation and a high dynamic range. Unlike the conventional approaches, this design uses a fully matched input stage, an unbalanced latch stage, and a two-clock operation scheme. A...
This paper presents an 11bit 200MS/s SAR-assisted pipeline ADC with a 2.5bit front end stage and two time-interleaved 9bit sub-SAR ADCs, implemented in 65nm CMOS process. The bias-enhanced ring amplifier works as the residue amplifier for power efficiency and large signal swing. Two self-biased inverter stages are designed in the ring amplifier to maintain the closed loop stability. The SAR ADCs with...
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