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We report an energy- and area-efficient modular analog front-end (AFE) architecture incorporating Δ-modulated ΔΣ (Δ-ΔΣ) signal acquisition for 1,024-channel brain activity monitoring platforms. The AFE employs spectrum-equalizing and continuous-time (CT)-ΔΣ quantization to make use of the inherent spectral characteristics of brain signals. The dynamic range (DR) of the neural signals has been compressed...
We present the first bi-directional neural interface chip that employs a stimulation artifact cancellation circuit to allow concurrent recording and stimulation. In order to further suppress cross-channel common-mode noise, we incorporated a novel common average referencing (CAR) circuit in conjunction with range-adapting (RA) SAR ADC for low-power implementation. The fabricated prototype attenuates...
The first (single-bit) feed-forward (FF) FIR DAC continuous-time (CT)-ΔΣ ADC is presented for cellular radio applications. It provides a robust loop delay compensation with no performance degradation in the presence of radio out-of-band blockers; a known drawback of FF CT-ΔΣ ADCs. At 20/30/40 MHz operation, the FOM is less than or equal to 36 fJ/conv. At 10 MHz operation, the FOM is 50 fJ/conv. The...
This work proposes an inductorless wideband low noise amplifier (LNA) for multistandard applications. This LNA is based on a self-biased complementary current-reuse common source amplifier on the forward path and a source follower on the feedback, using a gyrator-C like effect to create real valued impedance and an inductive effect, achieving wideband input matching. Designed in IBM 130 nm CMOS process,...
In this paper a highly-linear software defined radio front-end (LNA and Mixer) for wireless sensor networks in the 5.8-to-13 GHz frequency range is presented. It is suitable to IEEE 802.15.4a and IEEE 802.15.4a and upcoming different standards. The RF front-end features a very high robustness to out-of-band interference (OBI) thanks to mixer-based RF blocker filtering. This allows to remove any dedicated...
The recent surge of implantable and wearable medical devices have paved the way for realizing intra-body networks (IBNs). Traditional RF-based techniques fall short in wirelessly connecting such devices owing to absorption within body tissues. A different approach is known as galvanic coupling, which employs weak electrical current within naturally conducting tissues to enable intra-body communication...
In this paper, fractional spur suppression techniques for all-digital PLLs (ADPLLs) are summarized. The attention is paid to the recently proposed digital-to-time converter (DTC)-based ADPLL architecture. DTC's nonlinearity dominates the fractional spurs contribution. Its influence is modeled with a pseudo phase-domain ADPLL and its relationship with the spur level is quantitatively described. An...
This paper contains the development and verification of low noise amplifier stages (LNA) within the framework of a front-end for digital satellite radio diversity receiver operating around 2.3 GHz. First, a low noise high gain LNA is developed to reach the high requirements of satellite radio reception. Therefore a single-ended cascode architecture is chosen. The simulated noise figure is 0.58 dB...
This paper presents analysis and design of source inductance for multistage LNA at 77-GHz band in 90 nm CMOS technology. Instead of simultaneous noise and impedance matching, the analysis shows the optimum degeneration of the single stage design for millimeter-wave frequencies. A low-power 77-GHz band LNA has been demonstrated to verify the optimization result. By using the proposed method, the LNA...
Ultra wideband radar implementations for millimeter-/microwave operation are emerging in CMOS requiring high bandwidth. A distributed amplifier (DA) topology for use as low-noise amplifier (LNA) in nanometer CMOS, is explored in this paper. Important modifications like direct termination is beneficial both in area and gain linearity. A 5-stage amplifier provides a −3dB bandwidth of 36.5GHz and a S...
An improved recycling folded cascode operational transconductance amplifier with gain boosting and enhanced phase-margin is proposed. Among four variants of folded cascode amplifiers that have been implemented in TSMC 0.18μm CMOS process under same power and area constraints, the proposed amplifier achieves the lowest settling error of less than 0.5% compared to 1.1% settling error by Improved Recycling...
In this paper, an 8-channel low-power analog front-end amplifier (AFEA) with time-constant-enhanced topology is proposed for neural signal acquisition. The AFEA is composed of eight time-constant-enhanced amplifiers (TCEAs) and high-pass filters (HPFs), a multiplexed transconductor (MGM) and a transimpedance amplifier (TIA). The AFEA is designed and simulated in 65nm CMOS technology. The bandwidth...
This paper presents the design of a fast-settling reference voltage buffer (RVBuffer) which is used to buffer the high reference voltage in a 10-bit, 50 MS/s successive approximation register (SAR) ADC implemented in 65 nm CMOS. Though numerous publications on SAR ADCs have appeared in recent years, the role of RVBuffers in ensuring ADC performance, the associated design challenges and impact on power...
This paper combines the benefits of the Sturdy-MASH delta-sigma modulator with the benefits of the noise-shaped integrating quantizer. By using the noise-shaped integrating quantizer, the first stage quantization error is directly extracted in time-domain without the need for any extra hardware. This removes the loading on the first loop filter, and allows accurate inter-stage gain scaling. The second...
The paper describes the design of a differential broadband LNA covering the frequency range from 800 MHz to 5 GHz in 65nm CMOS technology. The work proposes a novel linearization technique for high-frequency wide-band applications using an active feedback as post-distortion. The technique is applied to a wide-band differential common gate (CG) LNA employing noise cancelation method. Post-layout simulations...
This paper describes the design and implementation of a fully integrated Tx/Rx front-end interface for Doppler Imaging with Piezoelectric Micromachined Ultrasonic Transducer (pMUT). The 4-Level Time Gain Compensation (QL-TGC) readout channel with an integrated biasing bank reduces Rx power with satisfactory noise performance (NF=17) and minimal area. The 65nm CMOS chip occupies 200 × 300 μm and has...
A novel receiver front-end is proposed for FM/FSK modulated signal, which is transmitted from a body worn device in the MedRadio spectrum of 401–406 MHz. The front-end comprises a low noise amplifier (LNA), a zero crossing detector (ZCD) and a frequency to digital converter (FDC). The proposed architecture offers direct digitization of the input signal and is immune to LO leakage and problem of image...
Multi-delay predictive FIR filters utilizing a small number of multipliers are proposed. These filters are shown to have substantially lower noise gain than the standard minimum-length predictors using the same amount of multipliers. These filters are formulated for both arbitrary-order polynomial and sinusoidal signal prediction. The use of dynamic programming for the efficient optimization of these...
The block implementation [1] of the normalized least mean square (NLMS) algorithm has another parameter governing its convergence property. Controlling its block length enables to keep the estimation error at a desired level against the fluctuation of the power ratio of the reference signal to the noise [2]. This block length control technique can be also applied to improving the convergence property...
A low voltage instrumentation amplifier for sensing applications such as the detection of biomedical signals is proposed. Since biomedical signals are of low frequency and small amplitude, noise has to be taken into consideration. In addition, the bio-signal amplifier should meet low power and low noise demand. Based on the 1.8V post-layout simulations of the overall circuit, the power consumption,...
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