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This paper presents the design and electrical implementation of a Wilkinson analog-to-digital converter for imaging detectors based on the use of silicon photo-multiplier scintillators. A multi-channel architecture, which shares the ramp generator among the different channels, is used to maximize the sampling frequency with the minimum power consumption and silicon area. The circuit has been implemented...
An interesting style for SoC (Systems-on-Chip) circuit design is the GALS (Globally Asynchronous, Locally Synchronous) paradigm, but its major drawback shows to be the asynchronous interfaces, especially when the GALS system is applied to a multi-point topology. The asynchronous interfaces found in literature are based on port controllers and can be called asynchronous wrappers (AW). They are responsible...
Flash memory is widely used in many fields, but there are still some problems with the generation of test pattern. The working and testing method of the memory is complex, for large capacity memory, the workload of generating a test pattern by the method of using manually is prohibitive. And Simulation files may not be obtained from design companies by the reason of protection of intellectual property...
A CMOS sinusoidal signal generator based on discrete-time (DT) and continuous-time (CT) processing is proposed for electrical bioimpedance spectroscopy supporting beta dispersion range of tissues. Differential stepwise sine-like signals with oversampling ratio (OSR) of 16 are used for input signals. DT filters with OSR=16 are used to attenuate close-in harmonics of these input signals, and a CT transconductance-C...
With the ever growing complexity of hardware designs, their functional verification has become quite a challenge. Despite other techniques like emulation and formal verification methods, simulation continues to be the most common and primary technique to functionally verify the hardware design written in Verilog. Due to the limited computational resources, exhaustive testing of the present-age complex...
In this paper, we present an auto-calibrated process insensitive relaxation oscillator. A process sensitivity of 1.36% is achieved by automatically sensing the output clock frequency spread and alternatively adjusting the capacitor-used for charging and discharging. In addition, a time to digital converter is adopted for tuning the compensating capacitor. Moreover, the proposed oscillator with on-chip...
A multiplying delay-locked loop (MDLL)-based multi-phase clock multiplier is presented. The proposed clock multiplier provides 8-phase output clocks and achieves a frequency range of 0.6–1.0 GHz with programmable fractional multiplication ratios of N/M, where N = 4, 5, 8, 10 and M = 1, 2, 3. The proposed clock multiplier is implemented in a 65 nm CMOS process and occupies an active area of 0.01 mm...
The implementation of a digital four-level pulse-amplitude-modulation reduced-state sliding-block Viterbi detector (VD) with two substates and two embedded per-survivor decision-feedback taps operating at one-eighth of the modulation rate is described. Implemented in an experimental chip fabricated in 14nm CMOS, the VD is designed to recover data at 25.6 Gb/s over an emulated time-dispersive channel...
In this study, an algebraic security analysis of a random number generator (RNG) which is built on a double-scroll chaotic circuit is put forward. An attack system is proposed to discover the security weaknesses of the RNG. The proposed attack system is proved to be valid by showing its convergence to the targeted system. Here, a master-slave synchronization scheme, which takes only the RNG structure...
Analog-to-Digital Converters (ADCs) are essential blocks in digital signal processing (DSP) systems, software defined radio receivers (SDRs), and portable data acquisition systems. This paper introduces an 8-bit Time-based Analog to Digital Converter (T-ADC). This T-ADC utilizes an inherited sample and hold required to eliminate the dedicated power hungry sample and hold circuit. Moreover, a new design...
Evolutionary computation, learning theory, neural networks, and fuzzy logic, are just few of the disciplines known as computational intelligence. In today's science and technology, computational intelligence techniques are widely used. They make use of computers' storage-and-speed abilities to address complex mathematical problems, which are difficult to be solved by conventional mathematical reasoning...
An all-digital on-chip clock generator is proposed in this paper. It features the tolerance of process, voltage and temperature variation according to the special algorithm. The clock generator depends on CMOS standard delay cell without any external clock source, and the periods of CMOS standard delay cell are calculated by the linear polynomial fitting. The proposed on-chip clock generator has been...
FPGAs are widely used to integrate cryptographic primitives, algorithms, and protocols in cryptographic systems-on-chip (CrySoC). As a building block of CrySoCs, True Random Number Generators (TRNGs) exploit analog noise sources in electronic devices to generate confidential keys, initialization vectors, challenges, nonces, and random masks in cryptographic protocols. TRNGs aimed at cryptographic...
High throughput is the crucial parameter of the adaptive filters. Here, we present an adaptive block finite impulse response (FIR) filter with high throughput using the concept of distributed arithmetic (DA). In the proposed work, block processing is applied to the adaptive filters that has helped in improving the throughput. In this paper, computation of partial products of filter output takes place...
Subthreshold ultra-low-power passive RFID tag's baseband processor core design with custom logic cells is presented in this paper, based on EPC C1G2 protocol. To deal with the critical timing and wide-range-PVT variation problems of the processor at very low power supply, and for the consideration of limited availability of RF power, power-aware scheme is applied to the key modules, including PIE...
This work presents the use of a compact and cost-effective clock generator to be incorporated in a time-domain microwave medical device. We demonstrate the ability of the Adafruit Si5351 development board as an alternative to the currently used table-top Tektronix gigaBERT 1400. We demonstrate the ability to produce low-noise clock signals from the development board that allows for the proper triggering...
Low power and robust circuitry are permanent hots pots in VLSI design. Adiabatic logic is one of potential breakthroughs for these goals. Especially, designing reliable clock tree is very significant for adiabatic logic due to four-phase clocked power required for pipelined data transmission in adiabatic system. In this paper, we present analysis of charging speed and clock types that influence power...
In this paper a specific implementation of the transceiver controller is presented, based on a high speed serial interface (HSSI) protocol-JESD204B. The implementation of this protocol provides less pin counts, lower complexity and more accurate timing control than the traditional parallel data transportation from ADC to DAC. This paper gives a design of the transceiver controller and the verification...
A 100 Gb/s clock/data recovery circuit using a high-speed BiCMOS process is designed and simulated. In this circuit a half-rate 50 GHz clock signal, injected in parallel with the tail current of an LC VCO, locks to a 100 Gb/s input NRZ data signal. Inductive tuning for the frequency tuning of the VCO is employed, which gives a wide frequency tuning range while maintaining a constant quality factor.
This paper presents an implementation of a binary pulse-position modulator (2-PPM) for impulse-radio ultra-wideband (IR-UWB) systems, capable of producing an appropriate signal to drive the final output stage of an ultra narrow pulse generator. Compared to the usual circuits based on voltage-controlled delay lines, this novel scheme uses digital signal processing of the clock and data signals with...
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