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System-in-Package (SiP) is becoming more and more important in integrating functionality while reducing final product form factors and cost. This is particularly true for mobile applications where continued effort to achieve ever thinning products is continuously pushing development of new materials, components and assembly technologies. This presentation focuses on a SiP flip chip (FC) pad design...
Assembly process reliability for Optical Multi-Chip Modules (MCM) is studied and improved. In the optoelectronic (OE) chip assembly for the Optical MCM, the OE chip with Au stud bump is joined with Sn-Ag-Cu (SAC) soldered in a through-waveguide via on an organic substrate to obtain high optical coupling efficiency. Since solid-liquid diffusion of Au to molten SAC is rapid, and formation of brittle...
High-performance computing has been aggressively driving pitch and performance requirements for off-chip interconnections over the last several decades, pushing solder-based interconnections to their limits. The most leading-edge Cu pillar technology faces many fundamental challenges in scaling to pitches below 30um, in particular with stress management and increased risks of Au embrittlement as solder...
Network virtualization allows the co-existing of logical networks (virtual networks) on physical network (substrate networks). Virtual Network (VN) reliability is a critical problem for end-users and service providers. It aims to ensure service continuity even upon failure. As more and more VNs are created over substrate networks (SN), the failure of a single SN component may lead to the failure of...
The interest in wearable electronics has been rapidly increasing due to the high demands for various wearable devices such as smart glasses and smart watches which satisfy the needs of today's customers. Future wearable devices will require fully flexible chip packaging performance and also maintain stable electrical performance under repeatedly bending environment. To meet these requirements, ultra-thin...
This work presents the thermal reliability test results of a metaconductor device on a glass substrate. Custom thermal cycling testing between room temperature and 100 °C has been performed for both Cu/Ni and Cu/NiFe metaconductor based transmission lines. The overall electrical performance has been well preserved between 300 kHz and 12 GHz. After a high temperature annealing treatment with 400 °C...
X-Ray Diffraction (XRD) is a very efficient experimental tool for strain/stress analysis at different scales, which makes possible to carry out some mappings in complex 3D flip chip assemblies. First, with single crystal method, both the chip and the substrate have been analyzed at the same positions, considering a 1mm2 step, in order to quantify the level of stress inside. Then Kossel microdiffraction...
As power demands for microelectronic devices continue to rise, new techniques for heat dissipation require innovative fabrication solutions such as on-chip cooling methods. The mechanical reliability of these high-powered, high-pressure systems is particularly sensitive to the interfacial strengths within the microelectronic architectures. In research at Georgia Tech, on-chip cooling methodologies...
Wafer Level Package (WLP) demand has been increasing in proportion to cost competitive device's demand year by year. In order to manufacture the WLP which has higher reliability efficiently, assembly processes with Bump Support Film (BSF) and Backside coating tape has been developed. The BSF consists of Back Grinding tape (BG tape) for getting a function as a wafer thinning and Bump Support Layer...
There are increasing interest in high temperature endurable sensor or device packaging solution for a set of wide ranging applications that include oil and gas production or deep sea exploration, advanced automotive application, aerospace, more electric aircraft initiative (MEA) or engine health management (EHM) systems, geothermal energy harvesting as well as other renewable energy industries. Besides...
This paper proposes a method of improving power delivery in a CPU package substrate with multilayer thin film capacitors (TFCs). Because TFC embedded technology can reduce the inductance of power delivery path, it can stabilize the power supply to the CPU. Higher permittivity, thinner layer thickness and wider conductor plane area results in larger capacitance. To further stabilize the power supply,...
Expanding FOWLP (Fan-Out Wafer-Level Packaging) from mainly 2D single or multi die solutions to 3D stacked multi-die solutions with SMDs integration, is of crucial importance to meet the requirements arising from new markets such as IoT/IoE and Wearables. This drives the development of new capabilities and technology breakthroughs in the current FOWLP process. One of the most hailed capabilities of...
Fan-Out (FO) chip on substrate is one of the fan-out solution for package integration. This solution brings the short interconnection between die to die for excellent electrical performance. Fan-Out chip on substrate device provides excellent electrical performance in multi-die connection,. The multiple re-distribution layer (RDL) processing is implemented in advance multi-dies FO chip on substrate...
The evolution of industrial wireless sensor networks (IWSNs) is driven by various factory automation applications with strict demands on latency and reliability, which requires flexible network resource allocation to support diverse QoS requirements of different applications. To this end, we propose an application-driven virtual network embedding (AVNE) scheme to facilitate the QoS provisioning for...
3DIC technology has enabled scaling beyond the Moore's Law to achieve higher transistor count, increased functionality and superior performance. Additionally, this technology allows integrating heterogeneous components such as Processor, FPGA, GPU, Memory, Serdes, etc. on the same interposer die enabling faster computing through reduced latency. The yields on the 3DIC technology have matured and are...
Recently, the electronics industry is moved maturely on the mobile/tablet market. The next fast growing opportunity market will be the Internet of Things (IoT) and Wearable Deivces in the near future. This advanced technology/package need to provide the ideal solution for small form factor, thin profile, high electrical performance, multi-function integration and low cost are the most critical requirements...
3D IC packages with stacked silicon interconnects (SSI) have many performance advantages over conventional flip chip packages. Using SSI, various die using the same or different technology can be connected to each other with the use of an interposer. The interposer allows a large number of die-to-die connections, enabling higher interconnect bandwidth, lower power consumption, and lower I/O latency...
For years the IC industry has been driven by Moore's Law and the functionality that fits in a single die will double every 18 to 24 months. As minimum dimensions have shrunk from 28 to 20 to 16nm and now to 7nm, supposedly die size should shrink accordingly. But for the application of networking, things don't go that way. Nowadays we are in an era that the demand to improve networking performance...
This paper demonstrates the high frequency performance and thermo-mechanical reliability of through vias with 25 µm diameter at 50 µm pitch in 100 µm thin glass substrates. Scaling of through via interconnect diameter and pitch has several electrical performance advantages for high bandwidth 2.5D interposers as well as mm-wave components for 5G modules. This paper focuses on the assessment of thermo-mechanical...
In recent years, continuing enhancement of highly-functional electronic devices, such as mobile terminal devices, has significantly increased the volume and speed of data transmission. This made high-frequency communication for data transmission between electronic devices essential. Thus, device component suppliers must offer products with low transmission loss in high-frequency range. An insulating...
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