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FinFET is the most promising double-gate transistor architecture to extend scaling over planar device. We present a high-performance and low-power FinFET module at 25 nm gate length. When normalized to the actual fin perimeter, N-FinFET and P-FinFET have 1200 and 915 ??A/??m drive current respectively at 100 nA/??m leakage under 1V. To our knowledge this is the best FinFET drive current at such scaled...
Ge/Si core/shell gate-all-round nanowire pMOSFET integrated with HfO2/TaN gate stack is demonstrated using fully CMOS compatible process. Devices with 100 nm gate length achieved high ION of ~946 ??A/??m at VG - VT = -0.7 V and VDS = -1 V and on/off ratio of 104 with decent subthreshold behavior. Significant improvement in hole mobility and ballistic efficiency is demonstrated as a result of core/shell...
The highest electron mobility in Ge NMOS to-date, ~1.5 times the universal Si mobility, is demonstrated experimentally. Gate stack engineered with ozone-oxidation is integrated with low temperature S/D activation to fabricate Ge NMOS. Mechanisms responsible for poor Ge NMOS performance in the past are investigated with detailed gate dielectric stack characterizations and Hall mobility analyses for...
This work reports on gate voltage dependent source and drain series resistance and associated barrier height in modified double gate Schottky MOSFETs with dopant segregation. We show that in our devices the series resistances is significantly reduced by lowering the Schottky barrier height (SBH). The series resistance and the barrier have been extracted using an external series resistance method and...
FinFETs with 1 mum tall fins have been processed on (110) bulk silicon wafers using crystallographic etching of silicon by TMAH to form fins with nearly vertical sidewalls of an (111) surface orientation. The concept of tall, narrow fins offers more efficient use of silicon area and better performance of multi-fin devices in high-frequency analog applications. N-channel FinFETs with 1.9-nm-wide fins...
Physics and technology of dopant-segregated Schottky (DSS) MOSFETs are reported. A novel approach to achieve low Schottky barrier height (phib) is proposed and demonstrated. The segregated dopants at the metal/semiconductor interface effectively modulate phib. The DSS junction significantly improves the current drivability of metal-source/drain transistors. We, for the first time, demonstrated CMOS...
There is great interest in SiGe/Si heterojunction tunnel diodes for novel devices such as sharp subthreshold slope MOSFET's. High tunneling current densities are a clear goal (for MOSFET drive current, e.g.). This work presents two clear results: (i) a direct measurement of the dependences on bandgap (Ge fraction) of the direct tunneling current vs. the "excess" defect-assisted tunneling...
InGaAs has been extensively studied as a potential channel material for sub-22nm gate length VLSI MOSFETs because of its low electron effective mass (m ) hence high electron velocity (v). At sub-22 nm gate lengths, a maximum 1 nm EOT dielectric and 5 nm thick channel with strong vertical confinement are required for high subthreshold slope and acceptably low drain induced barrier lowering (DIBL)....
A scalable, self-aligned In0.53Ga0.47As MOSFET process was developed and enhancement mode device operation was demonstrated. The 0.7 mum Lg device shows a maximum drive current of 0.14 mA/mum at Vgs=4.0 V and Vds=2.5 V. The devices have almost an order of magnitude larger drive current than our previously reported MOSFETs. The channel layer was 5 nm thick InGaAs with InAlAs bottom barrier for vertical...
We report the first demonstration of a surface channel inversion-type In0.53Ga0.47As n-MOSFET featuring gold-free palladium-germanium (PdGe) ohmic contacts and self-aligned S/D formed by silicon and phosphorus co-implantation. A gate stack comprising TaN/HfAlO/In0.53Ga0.47As is also featured. Excellent transistor output characteristics with high drain current on/off ratio of 104, high peak electron...
This paper demonstrates the integration of Al segregated NiSi/p+-Si S/D contact junction in p-FinFETs for parasitic series resistance reduction. Al is introduced by ion implant into p+ S/D region followed by nickel deposition and silicidation. Drive current enhancement of ~15 % is achieved without any degradation of short channel effects. This is attributed to the lowering of PhiBp of NiSi on p-Si...
We report in this paper the fabrirication and the characterirization of FDSOI pMOSFETs with metallic source and drain exhibiting the best performance obtained so far on metallic source/drain devices, with Ion=345 nA/mum and Ioff=30 nA/mum at -1 V for a 50 nm gate length device. These results have been achieved thanks to a careful optimization of the source/drain to channel contacts, which can allow...
In this work we use a full 3D Non-Equilibrium Green Function formalism in the effective mass approximation to calculate the resistance and resistivity of a thin silicon nanowire transistor and a doped silicon nanowire. The Non-Equilibrium green function equations are solved self-consistent with the Poisson equation. The resistances are calculated by averaging the resulting currents from an ensemble...
We report the results of a systematic study to understand low drive current of Ge-based nMOSFET. The poor electron transport property is primarily attributed to the intrinsically low density of state and high conductivity effective masses. Results are supported by interface trap density (Dit) and specific contact resistivity (rhoc), which are comparable (or symmetric) for both n- and p-MOSFETs. Effective...
We have developed a novel dual phase-modulated Ni silicide for Schottky barrier and series resistance reduction in dopant-segregated source/drain (DSS) n-MOSFETs. Using pre-silicide N2+ implant (thereafter N-implant), it is possible to selectively form interfacial epitaxial Si-rich NiSi2, reducing electron Schottky barrier(SB) from 0.7 eV to 0.34 eV while maintaining a low resistive bulk NiSi, at...
We demonstrated for the first time the device performance of (110) nMOSFETs featuring a Si migration process, resulting in better mobility and modified shape of the narrow active region, and ultra-shallow Al implantation after nickel silicide (NiSi) formation, resulting in reduced parasitic resistance. We found that these processes made the performance of (110) nMOSFETs competitive with that of (001)...
After forty years of advances in integrated circuit technology, the scaling of Silicon Metal Oxide Semiconductor Field Effect Transistor (MOSFET) has entered the nanometer dimension with the introduction of 90 nm high volume manufacturing in 2004. Presently at 45 nm going to 32 nm node in 2009, the latest technological advancement has led to low power, high-density and high-speed generation of microprocessors...
The parasitic resistance of the FinFET is investigated by the measurement based analysis. The RS/D model suggests that careful optimization as to the NiSi incorporation is necessary for the effective Rp reduction. The Rext seriously increases the Rp for TfinLt25 nm and also causes the Rp variability due to the Tfin variation.
Polish Government Program ldquoNew technologies based on silicon carbide and their applications in high frequency, high power and high temperature electronics rdquo covers an project package that consists of three general tasks. The contribution presents the overview of projects in the field dealing with the design and manufacturing of power SiC semiconductor devices.
We have successfully fabricated uniaxially strained SOI FinFETs with high electron mobility and low parasitic resistance. The electron mobility on (110) sidewall surfaces was found to surpass the (100) universal mobility by the subband engineering through uniaxial tensile strain along <110>. Thanks to this high electron mobility enhancement and the relatively low parasitic resistance, high I...
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