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Ensuring accurate testing of a UHF electronic package is the main requirement for a testing system. There are two problems: metrological certification as generator devices generating test pulses of desired amplitude and at a desired moment of time and the problem of measuring amplitude and time parameters of signals at the outputs of an electronic package. This paper observes the methods of measurement...
This paper proposes a power-efficient capacitor-array-based digital-to-time converter (DTC) using a constant-slope approach. Fringe-capacitor-based digital-to-analog converter (C-DAC) array is used to regulate starting supply voltage of the constant slope fed to a fixed threshold comparator. The proposed DTC consumes only 15 μW from a 1V supply, while achieving fine resolution of 103 fs when running...
The method of adaptive compensation of echoes in the range of significant delay values of telecommunication systems of loudspeaker communication is investigated. It is shown that it is possible to ensure a high rate of convergence and a high degree of echo cancellation in the formation of adaptive filtering in a localized neighborhood of delays.
In this paper, we propose a novel 24-transistor change-sensing flip-flop (CSFF) for ultra-low power applications. With the aid of an internal change-sensing unit, the proposed CSFF eliminates redundant transitions of internal clocked nodes when there is no change in the flip-flop content. No additional transistors are required compared to the conventional transmission-gate flip-flop (TGFF). Measurement...
This paper proposes a novel method to derive the junction temperature of a Silicon Carbide Schottky Barrier Diode (SiC SBD) when it is in operation. There is a correlation between the switching waveforms and the temperature, due to the material parameters and the carrier vary with the temperature. Estimating the Turn-on-delay time as a temperature sensitive electrical parameter (TSEP), the chip temperature...
This paper presents a low-power all-digital first-order single-bit delta-sigma time-to-digital converter (TDC) with a differential bi-directional gated delay line time integrator. The differential time integrator features low power consumption accredited to the use of only one bi-directional gated delay line in performing time integration, full compatibility with technology scaling, rapid time integration,...
An energy-efficient self-charged crystal oscillator (SCXO) employing a quadrature-phase shifter is proposed to provide wide-range pulse injection timing for power consumption reduction. The passive resistors of quadrature-phase shifter can be shared by the startup circuit to save area consumption. The double-edge extractor and the low-power comparator are added to reduce the power consumption. The...
Consideration was given to construction of a robust control law for a class of scalar nonlinear dynamic plants under conditions of uncertainty and saturation of a control signal. The synthesis of the control law relies on the hyperstability criterion, L-dissipativity conditions and using in the main circuit an explicit reference model with two outputs and low-inertia filter-corrector.
Adders are the main components in digital designs not only in additions but also in filter designing, multiplexing, and division. The circuit performance depends on the design of base adder. The demand of high-performance VLSI (very large scale integration) systems is increasingly rapidly for used in small and portable devices. The speed of operation is depends on the delay of the basic adder and...
A MANET or Mobile Ad-Hoc Network is decentralized in nature and it is basically a collection of heterogeneous mobile nodes which are autonomous and can communicate among themselves over the wireless link. In this infrastructure-less network, all the nodes dynamically route the packets by themselves with help of some protocols for sending or receiving the packet information. The ZRP or Zone Routing...
We propose a new caching concept in which wireless nodes in Device-to-Device (D2D) network can cache the initialsegments of the popular video files and may share to users in their proximity upon request. We term this approach as Bootstrapping-D2D (B-D2D) system. Our findings suggest that caching only initial-segments creates a large pool of popular files, thus improving the probability of availability...
In this paper, new modulo 2n ± 3 multipliers using a binary signed-digit (SD) adder tree struture are proposed. At first, we present fast modulo 2n ± 3 additions with two times of SD additions, and no carry propagations will arise during the additions. So that the modulo 2n ± 3 adders have delay times, which are independent of the wordlength n. In the proposed multiplication algorithms, 2n–1 partial...
This paper presents an integrated Analog Delay Line (ADL) for analog RF signal processing. The design is inspired by a Bucket Brigade Device (BBD) structure. It transfers charges from a sampled input signal stage after stage. It belongs to the Charge Coupled Devices (CCD). This ADL is fully differential with Common Mode (CM) control. The 28nm Fully Depleted Silicon on Insulator (FDSOI) Technology...
Multiple Cell Upsets (MCUs) induced by ionizing radiation in memories are becoming more likely to happen due to the continuous technology scaling down. Error Correction Codes (ECCs) are applied for recovering the stored information into its original state providing reliable computer systems. Several ECC are able to deal with MCUs, however, the higher the robustness of an ECC, more area, and energy...
Asynchronous quasi-delay-insensitive (QDI) circuits are a promising solution for coping with aggressive process variations faced by modern technologies, as they can gracefully accommodate gate and wire delay variations. Furthermore, due to their inherent robustness, such circuits are also promising for deep voltage scaling applications, where delays are orders of magnitude larger. However, QDI design...
Integrated digital circuits are frequency capped by its heavily constrained paths between flip-flop stages. These so-called critical paths are highly susceptible to delay fluctuations leading designers to use guard-banding in order to avoid timing violations. Several effects can cause these variations, whereas aging is of rising importance. Many works have addressed this issue through monitoring of...
Digital circuit technologies at nanoscale levels increase the likelihood of permanent, transient and intermittent faults. As a result, the demand for fault tolerance strategies is the main subject of many types of research targeting System-on-Chip (SoC) designs. In particular, retransmission mechanisms are one of the most used solutions in the Network-on-Chip (NoC) operation, but these mechanisms...
The challenges of the Internet of Things (IoT) in an urban environment are driven by smart vehicles which need to be able to efficiently sense and communicate with other nearby vehicles. System-on-chip (SoC) applications in the automotive market have strict circuit performances and reliability requirements for a temperature range of up to 175 0C. This work proposes an analysis of latched-comparators...
A new method for reducing power and area of standard cell ASICs is described. The method is based on deliberately introducing clock skew without the use of extra buffers in the clock network. This is done by having some flipflops, called sources, generate clock signals for other flipflops, called targets. The method involves two key features: (1) the design of new differential flipflop, referred to...
This paper addresses the issue of lag consensus of the leader-following multiagent systems with communication delays and switching topologies. Lag consensus means that the states of the followers lag that of the leader. Based on the graph theory and the common Lyapunov-Krasovskii functional method, we design a protocol ensuring the lag consensus of multiagent systems with communication delays under...
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