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Synthesis and implementation are two fundamental steps of the hardware design. Mountains of work in this area synthesize and implement your design from Hardware Description Language (HDL) description to the target FPGA device. We present ISE plus Customized P&R, a tool-chain converting Verilog designs into XDL that contains Xilinx FPGA implement modules. A key aspect of this tool-chain is that...
As more commercial services are offered and provided on-line, tools to analyse their socio-economic impact are also needed. For instance, new services such as Spotify, Uber and AirBnB have been able to disrupt different sectors because they rely on combining new business models together with information and communication technology (ICT). For (traditional) enterprises, however, launching that kind...
Resistive RAM (ReRAM) is an attractive candidate for next generation embedded nonvolatile memory [1][2], with several advantages compared to conventional flash technology. First, ReRAM is a CMOS-compatible low temperature back-end of line (BEOL) memory. There is almost no mutual impact between ReRAM element and front-end CMOS devices during the wafer processing. Second, it only needs 2∼4 extra masks,...
Article is devoted to the system development allowing to restore the volume of the left ventricle of heart, to estimate final systolic and diastolic volumes on the basis of the sequence of MRT-images from a parasternal position of a short axis in the automatic mode. The realized system was built on convolutional neural networks, 500 patients were used for training, for testing 200.
Due to ongoing advancement in the technology known as the Internet of Things, different devices that utilize sensors have drawn a strong interest in the field of research and application in recent years. Hence, a specific device that could perform the overall operation and could process the data of the sensor platform known as microprocessor is also a requirement. Some existing general-purpose processors...
Stereo matching systems that generate dense, accurate, robust and real-time disparity maps are quite attractive for a variety of applications. Most of the existing stereo matching systems that fulfill to all of these requirements adopt the Semi-Global Matching (SOM) technique. This work proposes a scalable architecture based on a systolic array, fully pipeline. The design builds on a combination of...
The HEVC standard is one of the newest video coding standards developed to face the upcoming challenges concerning video processing. HEVC allows only one type of entropy encoder, which is the CABAC (Context Adaptive Binary Arithmetic Coding), responsible for the symbolic data representation in order to translate the final video bitstream to a smaller number of bits. This work presents hardware architecture...
This work presents a low-area scalable architecture for the Depth Modelling Mode 1 (DMM-1) encoder of the 3D High Efficiency Video Coding (3D-HEVC) standard, removing the refinement stage. This simplification causes a small BD-rate increase (0.09%) but a significant reduction in memory usage of 30%. The scalable architecture can support different block sizes. Synthesis results for ST 65 nm Standard...
Video coding has become widespread through mobile devices. At the same time, the adopted resolutions have been enlarged, demanding more coding efficiency and motivating the development of the new state-of-the-art standard, High Efficiency Video Coding (HEVC). However, to achieve the required efficiency the new standard greatly increased the computational intensity. That, allied to real-time constraints...
Nowadays, the amount of small devices performing any kind of Digital Signal Processing (DSP) has increased drastically. On the other hand, the limited energy available to such battery-powered devices is a real problem. In DSP applications, one of the most important operations is the Finite Impulse Response (FIR) filter computation. The main FIR filter characteristics are the linear phase and feed...
Many-core systems are increasingly popular in embedded systems due to their high-performance and flexibility to execute different workloads. These many-core systems provide a rich processing fabric but lack the flexibility to accelerate critical operations with dedicated hardware cores. Modern Field Programmable Gate-Arrays (FPGAs) evolved to more than reconfigurable devices, providing embedded hard-core...
This work presents a hardware implementation of the morphological reconstruction algorithm for biomedical images analysis. The morphological reconstruction algorithm is based on the Sequential Reconstruction (SR). In this case. a hardware architecture has been developed and implemented by mapping the SR algorithm into an Altera Cyclone IV E FPGA based platform. including a NIOS II processor. The developed...
The increasing resolutions combined with storage and processing limitations of mobile devices point to the need for new compression techniques for video coding. Meanwhile, to achieve higher compression rates without compromising quality, the coding process becomes more and more complex. In reference software of HEVC the most time consuming step is the execution of Motion Estimation (ME), which is...
Many-core architectures are similar to a computer network, where it is necessary to ensure the security during the execution of sensitive applications. This article discusses two security-related issues: the secure admission of applications and the prevention of resource sharing during their execution. The safe application admission is an open research subject for many-core systems. Although several...
This paper evaluates the efficiency and performance impact of a dual-core lockstep as a method for fault-tolerance running on top of FreeRTOS applications. The method was implemented on a dual-core ARM Cortez-A9 processor embedded into the Zynq-7000 APSoC. Fault injection experiments show that the method can mitigate up to 63% on the FreeRTOS applications. This result is very near to the mitigation...
The HEVC is one of the most recent video coding standards, developed in order to face upcoming challenges, due to higher video quality and resolution. One of the HEVC components is the entropy encoder, which consists only of the Context Adaptive Binary Arithmetic Coding (CABAC) algorithm. The CABAC algorithm imposes some severe difficulties in order to achieve increasing throughput, due to the high...
The demand for higher quality video has increased in the past few years, due to the huge amount of electronic devices that process digital video in even higher resolutions. For that purpose, video coding techniques are used, which have, as main goal, the reduction of the required representation to process a digital video. Furthermore, embedded hardware video solutions are sought for both industry...
A concatenated LSTM (Long Short-Term Memory) architecture for CHP (combined heat and power) heat load forecasting was presented. Firstly, input data was normalized and separated into historical climate and heat load data. Then feed the separated data into two LSTM neural networks. Finally, the two LSTM models were concatenated as inputs to another LSTM model followed by two dense layers. Relu function...
In this paper, we report on a proof-of-concept wearable prototype, called iSeiz, that can detect specific seizure activity, namely generalized tonic-clonic, in epilepsy patients. We first describe the high-level architecture of iSeiz, and then elaborate on its hardware and software features, including its robust and low-computational intensive real-time seizure detection algorithm (SDA), as well as...
Human action recognition is one of the most active research areas of computer vision. With the rapid development of deep learning, using neural networks to realize action recognition becomes a popular thesis. This paper proposes a self-learned action recognition method based on neural networks. The proposed method trains dictionaries with sparse autoencoder (SAE) and extracts the key frames with sparse...
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