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The development of sustainable and durable ultra-low-power SoC calls for flexibility integration in the design flow. Reconfigurable logic circumvents the intrinsic low speed performances of software processing in microcontrollers but FPGA fabrics to be embedded suffer from a high power overhead compared to dedicated ASICs. We show that, by combining a power-oriented implementation using multi-VT,...
A new camera technology for high-speed color scanning is presented that is based on a novel multi-line CMOS color image sensor. A pixel matrix consisting of multiple red-, green-, and blue-sensitive lines allows acquisition of dense RGB color information at every pixel location including the possibility of improving the signal to noise ratio by summing up multiple exposures in the analog domain of...
Mitigation of radiation effects is one of the major problems for space-borne computing platforms. The presented work proposes an approach for building reliable, hardware fault adaptive stream processing platforms for space applications. The proposed concept is based on architecture-to-fault adaptation by run-time hardware reconfiguration. The concept assumes representation of system components in...
An approach for cheap and deterministic control communication using Ethernet real-time control communication is presented. Field-programmable gate array (FPGA) technology, i.e Xilinx XC3S500E from the Spartan-3E family, is used to implement the Ethernet communication strategy. The unit is defined in Verilog using Xilinx ISE 11.1 software tools. Data packages are sent at well defined times to avoid...
As the size and complexity of embedded systems are growing, the area cost and performance of the LSI circuits are becoming more crucial. A critical bottleneck for them is interconnections such as multiplexers (MUXs). Thus, a hardware synthesis technique for reducing MUXs, especially during the earlier design phase, has been demanded. This paper presents a novel MUX reduction technique in high-level...
A data acquisition system to acquire and record the output signal of a pulse generator is described. The system was built around Xilinx FPGA interfaced to an embedded computer via the PC104 bus. The system dynamically adjusts parameters (such as time window, sampling interval, pulse repetition frequency, etc.) to satisfy performance requirements of ultra-wide band life detection radar. The system...
Providing high reliability for FPGAs is a demanding task, as such devices may be subject to faults in the configuration bitstream, altering the specified function. Traditional modular redundancy remains the most used technique, due to its high fault coverage and low performance overhead. When high availability and strict real-time deadlines must be considered, however, a short mean time to repair...
With ever increasing demands on spectral efficiency, complex modulation schemes are being introduced in fiber communication. However, these schemes are challenging to implement as they drastically increase the computational burden at the fiber receiver's end. We perform a feasibility study of implementing a 16-QAM112-Gbit/s decision directed equalizer on a state-of-the-art FPGA platform. An FPGA offers...
In this paper, we present a technology mapping and clustering tool for leakage power reduction in FPGAs with programmable, dual-VT logic blocks. The use of Reverse Back Bias (RBB) circuit techniques is recognized as one of the more promising strategies in mitigating leakage power, a critical problem in circuits deploying deep submicron process technologies. FPGAs with the ability to adjust fabric...
This paper describes an eleven channel artificial nerve signal generator with a programmable inter-channel time delay using only a Field Programmable Gate Array (FPGA) and a small number of passive external components. The FPGA is used to create a novel, linearised Pulse Width Modulation scheme which would not be possible with other alternatives technologies such as a micro controller. This signal...
A novel parallel semi-systolic semi-scanned array architecture is proposed for the implementation of four-dimensional (4-D) IIR filters. These filters have emerging applications in computed tomography (CT), volumetric ultrasound, and light field processing for computer vision. The proposed architecture can be applied to a broad class of 4-D IIR filters, and we show results for a frequency-planar depth-selective...
Structured ASICs are designed to bridge the gap between ASICs and FPGAs in terms of cost and performance. By predefining most of the manufacturing masks they highly reduce time-to-market (TTM), non-recoverable engineering (NRE) costs and lithography hazards while exhibiting higher performances than FPGAs thanks to hardwired configuration and interconnections.
As the complementary metal oxide semiconductor (CMOS) scaling become harder, researchers have been trying to improve field programmable gate array (FPGA) performance by utilizing nonvolatile memory devices. This paper reports on a novel FPGA architecture where nonvolatile memory devices are used as nonvolatile reconfigurable switches (NRSs). It has found that resistive change memory (RCM) can be utilized...
This paper introduces a novel Timing Generator Format Controller (TGFC) circuit that produces programmable multi-gigahertz signals with "timing-on-the-fly" capability. For the first time (we believe), timing edges can be programmed to occur at almost any point during the test, limited only by a minimum pulse-width (~70ps) and maximum sustainable data rate (~3.2Gbps in the prototype). Timing...
This paper mainly proposes a timing scheme of a digitally controlled DC-DC converter, which is described in hardware description language (HDL) at the functional level. FPGA is adopted for the optimization of computation, sampling and modulation to get precise and fast dynamic response of DC-DC converters. The concept of this timing scheme is broad and includes DPWM scheme, sampling scheme and computation...
Decimal arithmetic has gained high impact on the overall performance of today's financial and commercial applications. Decimal additions and multiplication are the main decimal operations used in any decimal arithmetic algorithm. Decimal digit adders and decimal digit multipliers are usually the building blocks for higher order decimal adders and multipliers. FPGAs provide an efficient hardware platform...
Field Programmable Gate Arrays (FPGAs) provides fast and low cost implementation of DSP systems. The increasing popularity of FPGAs and lack of experience of the DSP algorithm designers on HDLs, makes the High Level Synthesis tools vital for design, early performance estimation, prototyping, testing and verification. In this paper, we present a high-level design-time verifiable Register-Transfer Level...
A typical high-speed decoder implementation for an LDPC may require hundreds or even thousands of variable and check node processors. Since check node processing unit (CNPU) is far more complex than variable processing unit, hardware requirements of CNPU has a big impact on the final decoder complexity. Here, an FPGA implementation of the soft parity check node for min-sum LDPC decoders is analyzed...
Technology mapping is the first stage of the process of porting an application onto Field Programmable Gate Array (FPGA) architecture. This stage is highly critical as it sets the constraints of its successor stages of clustering, placement and routing. Intrinsic Shortest Path Length (ISPL) has been shown to accurately predict the post placement individual net length information for a given net list...
This paper presents a new approach for the high performance and hardware efficient design of coordinate rotation digital computer (CORDIC) processor structure. The proposed design approach completely eliminates the ROM requirement of constant arctangent values. Furthermore, efficient designs of carry look ahead adders (CLAs), exploiting one input as constant, in the angle adder/subtractor datapath...
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