The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This paper presents an innovative surface mount bottom power ground device consisting of a dual gate driver and two optimized MOSFETs in a single package to produce a high efficiency DC-DC synchronous buck power stage. The paper illustrates the structure of the new technology, novel assembly method, characterization of device, and explains the benefits of packaging technology in a DC-DC converter...
A low-cost and manufacturable 3D IC substrate-less Chip-on-Wafer (CoW) package has been studied. The new structure is a result of process simplification from the production-proven Chip on Wafer on Substrate (CoWoS™) technology. It features three layers of submicron (0.8µm pitch) Cu RDL on a Si interposer. High interposer yield is ensured with the excellent FAB-grade low defect density as demonstrated...
This paper is dedicated to the research and development of hermetic and biocompatible packaging of microelectronic devices for medical applications. Materials such as Al2O3, HfO2, TiO2, ZnO, SiN, SiO2, SiOC, SiC, a-CH, and BN which had been reported as biocompatible and compatible with fabrication in standard clean rooms were studied. As there were many candidate materials, a method for selecting...
In recent years, 2.5D packaging has quickly turned from a buzzword into an Advanced Packaging reality. Not dissimilar to the Multi-Chip-Modules (MCMs) of the past, 2.5D packages utilizing high density interposers with favorable electrical characteristics can be a cost efficient and high performance alternative to significantly more complex 3D or SOC integration schemes. Dictated by the trend towards...
Due to the extreme complexity of neuroscience and neurosurgery, there is naturally a need for probing systems with more functions which can probe in three dimensions. For instance, nerves can size differently in different locations and can present three dimensional neuro imaging with multiple recording and stimulating points, calling for the new developments in this emerging field. It is also highly...
With more implementation of LED in lighting and communication applications, increasing demand for function enrichment and miniaturization has emerged. Existed technologies are highly challenged. System-in-package (SiP) technology is very promising in terms of function integration and cost reduction. In this paper, a novel SiP platform for LED system with integrated driver and wireless control function...
This paper presents the first demonstration of an ultra-thin glass BGA package that is assembled on to mother board with standard SMT technology. Such a package has many new advances that include ultra-thin glass, high speed through via hole formation and copper metallization, double-side RDL wiring with a dvanced 3 micron ground rules, and Cu-SnAg microbump assembly of a 10mm silicon test die. Glass,...
Moore's law has been the foundation for increasing complexity and density of semiconductor chips and has prevailed over the years through many transitions in silicon (Si) nodes. The simultaneous scaling of density, cost and performance which is made possible by fan-out wafer level packaging may be viewed as the manifestation of Moore's law in the packaging domain. Recent developments in Fan-out Wafer...
The semiconductor industry continues to scale up silicon wafer size in an effort to drive lower costs associated with high volume manufacturing. This effort has begun in earnest at the SUNY College of Nanoscale Science and Engineering, driven by the Global 450 mm Consortium (G450C). The focus of the G450C is to be a public-private partnership (CNSE, Intel, TSMC, Samsung, IBM and GLOBALFOUNDRIES) that...
With the development of the integrated circuits, there is an inevitable trend in the development of the electronics industry, that the electronic devices become much smaller in shape, and integrated with higher density within, and more and more functionality. 3D SIP (System in Package) has become the mainstream technology for the microsystem integration. Meanwhile, the through silicon via (TSV) is...
Through-silicon via (TSV) technology has been the core of the next generation of 3D integration. Although some TSV reliability issues have been addressed in some literatures, but the sidewall scallop resulted from Bosch etch process has not been thoroughly investigated. In this paper, we focus on the effects of different sidewall scallops on the interfacial stress evolution. An axi-symmetric single...
This paper presents a novel spray coating process for the forming of sidewall insulation of through silicon via (TSV) which was a challenging process in CMOS image sensor (CIS) packaging. In conventional way, silicon oxide by plasma enhanced chemical vapor deposition (PECVD) is chosen as insulation material. In this paper, one kind of phenolic aldehyde polymer is deposited on the sidewall of though...
Wafer warpage in wafer level packaging process poses threats to wafer handling, process qualities, and can also lead to unacceptable reliability problems. With larger diameter wafer adopted, this issue becomes more serious. In the paper, a new designed trench structure was introduced in WLP process to reduce the final wafer warpage. Both experiment and simulation methods are used to investigated the...
Given the cost per transistor is to grow below 22nm node, SOC partitioning is emerging as a viable solution compared to a monolithic solution. Ubiquitous 2.5D/3D heterogeneous integration is evolving as an eminent approach to achieve lower cost, higher bandwidth, smaller footprint and lower power. System partitioning schemes and heterogeneous integration mechanisms directly impacts performance, cost...
Light Emitting Diodes (LEDs) as an emerging light source has been rapidly developed due to its considerable advantages including high energy efficiency, extremely long life and environmentally friendly. Since packaging accounts for the major part of the total cost, a novel molding process for wafer level LED packaging will be presented in this paper, which could decrease the total cost by the wafer...
Market size of high-brightness LED lighting has been rapidly growing upon the continual improvement of quantum efficiency and light extraction. However some key breakthroughs must be made before this technology can be fully adopted into the broad market, such as efficient thermal dissipation and low manufacturing cost. A major portion of cost of an LED module falls in the packaging processes after...
This paper introduces a new encapsulated WLCSP product (eWLCS). The new product has a thin protective coating applied to all exposed silicon surfaces on the die. The applied coating protects the silicon and fragile dielectrics and prevents handling damage during dicing and assembly operations, effectively providing a durable packaged part in the form factor of a WLCSP. The manufacturing process leverages...
Miniaturization and higher functionality have been and continue to be serious pursuits of the electronics industry. In relation to the miniaturization of package size, the 3D integration of devices using through silicon vias (or TSVs) is currently being researched extensively. 2.5D integration with a passive interposer is currently being researched as a step toward achieving the goal of complete 3D...
Three dimensional molded interconnect devices (MID) with fluidic features offer new possibilities for the packaging of microfluidic components. This paper reports about an MID based fluidic interposer to bridge the micro-macro gap of fluid delivery in microfluidic systems. The interposer is fabricated by standard MID fabrication technology and includes a metallization for electrical signals and channel...
The pace of change in packaging technology today has accelerated to the highest rate in history. This is driven by the penetration of electronics into virtually every segment of society. Communication, transportation, education, agriculture, entertainment, health care, environmental controls of heating, cooling and humidity, defense and research all rely heavily upon electronics today. This diversity...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.