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Silicon interposer has emerged as a substrate of choice for integrating fine pitch, high density devices. Conventional packaging of 2.5D/3D devices involves multiple level of assemblies. Normally, 2.5D/3D devices are first assembled on thinned silicon interposer with aspect ratio of 10:100 followed by second level assembly on a multi-layer organic build-up substrate. In this study we introduce direct...
Enabling single-mode photonic packaging in high-throughput microelectronic equipment can dramatically improve cost and scalability. We experimentally demonstrate such solution using 12-fiber interfaces and flipped-chip lasers. We measure −1.3dB peak fiber-to-chip transmission.
Conventional bonding techniques like fusion, glass frit, soldering, eutectic, and anodic bonding, have been used in packaging for micro-electro-mechanical systems (MEMS). These bonding techniques require high temperature which results in bending/buckling of MEMS devices especially in case of hanging structures. In this work, low temperature and low cost bonding techniques with commercially available...
Glass interposer is introduced as an alternative to silicon interposer for 3D integration due to the attractive advantages such as excellent electrical isolation, extremely low insertion loss, adjustable coefficient of thermal expansion (CTE), and most importantly low cost potential with the capability of large panel size fabrication. In this study, a novel scheme is proposed to fabricate glass interposer...
This paper will present wafer level packaging approaches and results for MEMS encapsulation and integration applied to resonators. The core technologies involve interposer fabrication with Through-Silicon Vias (TSV), temporary wafer bonding for thin wafer handling and wafer bonding for metallic sealing under vacuum and for formation of electrical interconnects. Seal rings based on AuSn metallurgy...
In this paper we have reported that a novel method to maintain alignment accuracy in wafer bonding process utilizing resin as an adhesive material. We have proposed tentatively localized bonding method with 1100 nm near infrared (NIR) irradiation that is transparent to Si wafers. With the aid of our localized tentative bonding process, we have achieved maintenance of alignment accuracy when the 100µm...
This paper demonstrates a five layers wafer level packaging. This technology has been specially developed for chip scale atomic clock system package. It includes a sealed vapor cell and two supports for vertical-cavity surface-emitting lasers and photodetector. The sealed cavity is achieved by Glass-Silicon-Glass (G-S-G) anodic bonding with high hermeticity, high reliability and low bonding temperature...
In this paper, we report a novel TSV fabrication method to develop CMOS image sensor package. The major processes comprise cavity wall formation, glass carrier to IC wafer bonding, grinding, TSV fabrication, passivation, laser drilling to expose the Al bondpads, PVD deposition, electroplating, re-distribution layer (RDL), under bump metallization and solder bump formation. The as-formed TSV CIS structure...
The advancement of package technology to enable die to die interconnects have allowed Integrated Circuit (IC) technology to progress into much higher density region. The fabrication process requires wafers to be processed at lower thicknesses while bonded to a carrier. The forces applied to the thin wafer often generate localized stress fields that cause Si defects to propagate in a form of cracks...
Three-dimensional integrated circuits (3D-ICs) packaging has attracted a lots of attentions due to it has advantages of integrating heterogeneous functions among stacked chips. The thermal mismatch stresses with regard to interconnects composed through silicon via (TSV) and microbump induced by thermal cycling loads becomes a serious concern while a thinner stacked die thickness is required. To shrink...
Currently packaging design needs more a computational processing roles and became the fundamental selling art of products. Design of packaging is very subjective and company needs to understand customer's behavior, perception and attractiveness. Challenges arise when marketing in fast moving consumer goods is getting very dynamic and competitive. Computational needs to identify customer's perception...
New System-in-Package (SiP) with innovative Wafer-Level-System-Integration (WLSI) technologies that leverage foundry core competence on wafer processes have been demonstrated. The WLSI technologies include Chip-on-Wafer-on-Substrate (CoWoSTM) 3DIC and interposer, Integrated Fan-Out (InFO) and Chip-Scale Wafer-Level-Packaging. Wide application portfolio from very low I/O pin-count, low-cost devices,...
Fibre optic interconnection processes and hybrid integration of electronic devices for highspeed Si photonic systems are presented. An overview of ePIXfab which offers affordable access to an advanced Si photonic foundry service is also presented.
As the market drives electronic products to be smaller and faster, designers must use advanced packaging technologies. In many cases, these technologies are significantly more expensive than traditional packaging, but are necessary to meet the product requirements. Both fan-out wafer level packaging and 2.5D packaging on a silicon interposer enable designers to package multiple die in close proximity...
Through-silicon via (TSV) technology has been the core of the next generation of 3D integration. Although some TSV reliability issues have been addressed in some literatures, but the sidewall scallop resulted from Bosch etch process has not been thoroughly investigated. In this paper, we focus on the effects of different sidewall scallops on the interfacial stress evolution. An axi-symmetric single...
Wafer warpage in wafer level packaging process poses threats to wafer handling, process qualities, and can also lead to unacceptable reliability problems. With larger diameter wafer adopted, this issue becomes more serious. In the paper, a new designed trench structure was introduced in WLP process to reduce the final wafer warpage. Both experiment and simulation methods are used to investigated the...
With the development of the integrated circuits, there is an inevitable trend in the development of the electronics industry, that the electronic devices become much smaller in shape, and integrated with higher density within, and more and more functionality. 3D SIP (System in Package) has become the mainstream technology for the microsystem integration. Meanwhile, the through silicon via (TSV) is...
This paper presents a novel spray coating process for the forming of sidewall insulation of through silicon via (TSV) which was a challenging process in CMOS image sensor (CIS) packaging. In conventional way, silicon oxide by plasma enhanced chemical vapor deposition (PECVD) is chosen as insulation material. In this paper, one kind of phenolic aldehyde polymer is deposited on the sidewall of though...
In this paper a new packaging technique based on Selective Laser Melting is presented which tries to replace solder or sinter layers, respectively bond wires. Following the intended contact geometry and concept, simulations show the influence of the contact geometry on the thermo-mechanical stress the device is committed to. First investigations on the constraints of the production process are represented...
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