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Silicone-cycloaliphatic epoxy resins were successfully synthesized by a two-step reaction route: (i)hydrosilylation of 1,3,5,7-tetramethylcyclotetrasiloxane (TMCTS) and 2-epoxy-4-vinyl-cyclohexane,and then blocking of unreacted Si-H with n-butanol, (ii) In order to reduce the viscosity, different amounts of active diluent(Allyl Glycidyl Ether) was added into(i). The molecular structures of the hydrosilylation...
The trends for smartphone and other mobile devices are more than ever for integration and lower cost. Meanwhile, a higher degree of functionality and performance, thinner profile, and longer battery life are some of the additional market drivers seen in these devices. The implications of these market drivers on the packaging content of mobile devices including internet of things (IoT) and wearable...
Through silicon via (TSV) technology offers a promising approach to achieve three dimensional integrated circuit integration. Via-last TSV process has the advantages of flexibility and lower cost. In this paper, we report our latest progress on wafer level packaging by via-last process. The 200mm device wafer was bonded with a carrier wafer. Then, the vertical TSV structure with aspect ratio of 3∶1...
In order to achieve the packages with much higher performance, more I/Os, lower profile and lighter weight, the thickness of silicon wafer has been decreased dramatically in recent years, but which degrades the strength of thinned wafer. In this paper, three-point bending test was adopted to evaluate the thinned wafer fracture strength, and the impacts of back-grinding process parameters on the wafer...
The rapid development of gallium nitride (GaN)-based wide bandgap power devices has been stirring power electronics industry for almost a decade. Advanced packaging solutions are eagerly needed to exploit the maximum potential of the high performance GaN semiconductors. Especially for devices in the cascode configuration, the design and fabrication of a suitable package are very challenging for high-frequency,...
The EMIB dense MCP technology is a new packaging paradigm that provides localized high density interconnects between two or more die on an organic package substrate, opening up new opportunities for heterogeneous on-package integration. This paper provides an overview of EMIB architecture and package capabilities. First, EMIB is compared with other approaches for high density interconnects. Some of...
MEMS devices are continuous evolving to achieve smaller size and lower cost with improved performance. The Through silicon via (TSV) technology offers a promising approach from the perspective of MEMS device packaging and integration. In this paper, we report our latest progress on wafer level packaging of MEMS devices by via-last process. The 200mm MEMS wafer was bonded with a glass cap wafer. Then,...
This paper presents buckled nitride thin-film encapsulation using anti-adhesion layer assisted transfer technique and BCB/nitride bilayer wrinkling due to elastic property mismatch between the two attached materials. A 900 nm silicon nitride film is deposited on a Si carrier wafer coated with hydrophobic monolayer and then non-patterned nitride film is directly bonded to BCB sealing rings prepared...
The emergence and evolution of any package technology is driven by market trends as experienced by the end application. With the maturation of the mobile market, the trends for Smartphone and other mobile devices are more than ever for lower cost. Meanwhile, a higher degree of functionality and performance, thinner profile, and longer battery life are some of the additional market drivers seen in...
This paper describes and demonstrates a high-throughput strategy for making fan-out packages for very small, sub-millimeter, devices. First, micro-transfer printing was used to deterministically assemble large arrays of devices, face-up, onto 200 mm wafers. The devices used in this study were 80 um x 40 um chips with a redistribution metal and six contact pads designed to be used as an electrical...
Following the recent trend of miniaturization of MEMS and the approach to improve the comfort of medical implants for patients by reducing their size the polymer Parylene is a promising candidate for encapsulation issues. Parylene combines a number of excellent properties like biocompatibility / biostability, chemical inertness, transparency and low water permeability. Within the presented work the...
This paper reports fabrication of CMUT (Capacitive Micromachined Ultrasonic Transducer) based forward looking ultrasonic endoscope using custom designed LTCC (Low Temperature Co-fired Ceramic). Bottom electrodes and cavities are separately patterned on LTCC and SOI wafers, respectively. LTCC wafer is used as bottom substrate (prime wafer) for anodic bonding and ring array and linear array CMUTs transducers...
This paper proposes a combination of annular copper and cylindrical copper as the TSV conductor to decrease the effect of thermal mismatch between copper and silicon in MEMS packaging, which results in a reliability risk between redistribution layer (RDL) and TSV. There are three important factors which may have the most serious influence on the reliability being simulated and analyzed. They are the...
The purpose of this study is to evaluate the strength of TSV silicon chips using a point-load on elastic foundation (PoEF) test, associated with an acoustic emission (AE) method for detecting local material cracks or delamination occurring during the test before the chip breaking (or catastrophic failure). The results indicate that there are no larger-than-25 dB AE signals and no via cracks occurring...
In recent years, demand for high density integration of semiconductor chips has steadily increased due to miniaturization and high-performance requirements of electronics including Smartphones and Tablet PCs. In addition to 3D integration using Through Silicon Via (TSV) technology and 2.5D integration technology using silicon interposers, Fan-Out Wafer Level Packaging (FOWLP) using redistribution...
This paper is on a vertical through silicon via (TSV) fabrication method of integrated circuit (IC) packages. The vertical TSV processes are developed by evaluating different via depth and diameter. The stress simulation and analysis of the as-formed vertical TSV structure are also conducted to predict the possible mechanical failure during the reliability test.
High voltage LED (HVLED) is a LED chip configuration that comprises multiple LED units in series, and offers higher luminous output than that of conventional LED chip configurations. Due to the high luminous output and, accordingly, an elevated junction temperature, the thermal performance of HVLED must be enhanced by the flip chip assembly with high-thermal conductivity underfill. To maximize the...
This paper reports a tri-fold inertial measurement unit (IMU) that is fabricated with a batch-mode 3-D assembly process. Each chip of a tri-fold die includes a single axis z-gyroscope and 0–2 lateral-accelerometers. The tri-fold dies are batch-mounted on sidewalls of silicon cavities on a wafer to form 6-axis IMUs. The accelerometer has a measured bias instability of 6.8 µg and a noise floor of 66...
Today's packaging standard for consumer MEMS sensors are plastic mold packages of the LGA or QFN type. Multiple chips are placed on a substrate or leadframe, electrically connected by wire bonds and protected by overmolding the sensitive devices. While being a flexible and very effective packaging technology it contributes significantly to the overall sensor dimensions in x-, y- and z-direction. The...
The paper describes three-dimensional, dynamic finite element simulations of wire bonding processes on silicon dies, which are bonded on soft interposers by soft adhesives. The application of soft materials below a die has increased e.g. due to a reduced influence of the substrate stiffness on a sensor chip. However, a soft die bond may cause trouble during the subsequent wire bonding process, because...
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