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Comprehensive investigations were conducted on identifying integration efforts needed to adapt plasma dicing technology in BEOL pre-production environments. First, the authors identified the suitable process flows. Within the process flow, laser grooving before plasma dicing was shown to be a key unit process to control resulting die sidewall quality. Significant improvement on laser grooving quality...
A density staggered cantilever was developed to measure the micron length gravity between itself and an optically levitated microsphere in high vacuum. The cantilever, has two main density contrasted materials gold(19.3g/cm3) and silicon(2.33g/cm3), where each of the material is finger-shaped and stagger placed next to each other, constitute an integral finger array on the device layer of SOI wafer...
To confirm the effectiveness of the via-last through silicon via (TSV) process consisting of notchless Si etching and wet cleaning of the first metal layer, we evaluated the metal contamination caused by this process. The metal contamination generated near the TSV was investigated by measuring the reverse-bias leakage current of n+/p diodes placed near the TSV. The TSV diameter was 6 µm and the n+/p...
Quartz due to its piezoelectricity and its good temperature stability is one of the most used materials in devices for time-frequency applications. Quartz resonators are generally obtained by chemical etching or chemical mechanical polishing but these two methods do not allow the shrinking of the dimensions of the devices and limit reachable geometry: in particular structures with high aspect ratios...
This paper presents the methods of eliminating the plasma-induced Si substrate damage in periphery regions, resulting from high aspect ratio etching process for 3D NAND fabrication. The impact of Si substrate damage is verified by the low and high bias power experiments. The result indicates more Si damage is present with high energy bombardment; therefore, high bias power is recommended to be inhibited...
In this work, a novel imaging photoluminescence-based metrology method is introduced, with potential application to buried defect detection in silicon devices during semiconductor manufacturing process. The theoretical and practical aspects are both discussed. A new metrology tool was realized and thoroughly tested through real-life semiconductor samples to reveal the capabilities of the suggested...
Due to its independency to the substrate used, Soft mold NanoImprint Lithography (S-NIL) is a technique of great interest in particular for the fabrication of optical devices. We demonstrate a mature pathway for the realization of optical filters from the conception to the optical characterization. Those filters can be realized on large surfaces (up to 6″ diameter wafers) with high conformity on various...
Silicon nanowire (SiNW) arrays are demonstrated as a suitable substrate for the preconcentration of trace nitroaromatic compounds and subsequent desorption via Joule heating of the array. Arrays are fabricated from Si wafers containing epitaxially grown layers of high conductivity p-type Si, with a relatively low conductivity intrinsic Si layer. Arrays are fabricated using a combination of nanosphere...
We propose a wafer-scale technique for nanostructure formation inside vertically oriented, through-membrane nano-pores. It uses 50 nm monocrystalline silicon pillars as a mold, embedded in a silicon nitride membrane formed in an innovative step. The proposed technique paves the way towards advanced functionalization of parallel oriented nano-pores for actuation, sensing, filtering/trapping purposes.
This paper presents a monolithic approach for the integration of silicon nanowires (Si NWs) with microelectromechanical systems (MEMS). The process is demonstrated for the case of co-fabrication of Si NWs with a 10-µm-thick MEMS on the same silicon-on-insulator (SOI) wafer. MEMS is designed in the form of a characterization platform with an electrostatic actuator and a mechanical amplifier spanned...
A method for fabrication of VeSFETs, three-dimensional fin-type MOS transistors is presented. The VeSTIC process was developed and experimentally implemented in ITE. The test devics were manufactured, and their electrical characteristics were measured. Methods for extraction of a set of the VeSFET physical parameters are proposed based on the device compact model. The flat-band voltage, mobility and...
Textured ultra-thin silicon wafers were obtained by means of chemical etching in potassium hydroxide solution. The surface morphology and roughness of ultra-thin silicon wafers were investigated depend on their thickness, doping level and texturing. Based on thinned silicon substrates the heterojunction solar cells were produced. It was determined clear dependence of photovoltaic properties on surface...
This work includes design of microwave plasma source, ICP chamber, laser scribing trials, development of the water soluble mask material and DRIE process. Electron cyclotron resonance (ECR) plasma sources are used for a variety of materials processing applications such as semiconductor etching and deposition. ECR sources has several advantages over reactive ion etchers (RIE) commonly used since the...
The article examines physical principles, conceptual design and fabrication of integrated pressure transducer manufactured by means of microelectronic technology — MEMS and its optimization questions. Spatial distribution of the intrinsic stress caused by the transducer manufacturing and its current heating by supply current was studied by the method of modulation polarimetry.
We propose an arrayed test structure to assess the damages of metal-oxide-semiconductor field-effect transistors (MOSFETs) exposed under back-side LSI processes, such as by Focused Ion Beam (FIB). Back-side process with FIB is becoming essential to analyze and repair modern LSI chips, to avoid processing through many metal layers with dense wiring and dummy patterns. To access transistors from back-side,...
This paper presents a novel, versatile process for the fabrication of wide and deep cavities for silicon MEMS devices without the need for wafer bonding. Instead of filling large trenches with sacrificial materials before encapsulation or directly using wafer bonding, we present a method that utilizes isotropic etching with XeF2 gas through a thin silicon dioxide film prior to the deposition of encapsulation...
This paper presents a micormachined quarter wavelength monopole antenna operating at the millimeter wave band for automotive radar application, specifically at 77 GHz. The antenna will be realized using surface micromachining on a low resistive thick silicon substrate and fed by coplanar waveguide. Bulk micromachining is used to etch silicon underneath the antenna in order to reduce the Ohmic losses...
An inductively-coupled plasma-reactive ion etching system (ICP-RIE) for a half-inch wafer process is developed. The machine is in human-size and supporting clean-localized manufacturing system of minimal fab. A tiny chamber with a volume of 1/41 enhances performance of gas-replacement inside the etching chamber. The gas switching time between etching and polymeric passivation for a Bosch process at...
In this work we present the first steps towards achieving Photonic Crystals (PCs) operating in the Near-Infrared (NIR) wavelength range using Macroporous Silicon (MPS). The MPS structures herein shown are fabricated using Electrochemical Etching (EE) of silicon. Pores are arranged in a square lattice of 500 nm periodicity and pore size is around 200 nm to 350 nm. Preliminary results show straight...
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