The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
High-frequency isolated DC-DC converters are gaining momentum in applications where the demand of isolation matches with that one of compact and light equipment. A seminal topology, constituted by two bridges operating at high frequency and coupled by a transformer, has emerged as an attractive solution that fulfills the above-mentioned demands. The two most popular versions of such a topology are...
In this paper a novel multilevel voltage source inverter topology is proposed for high power applications requiring expensive switching component such as, traditional Silicon, and/or newly-evolving Silicon Carbide, and/or Gallium Nitride based power semiconductor transistors. This multilevel voltage source inverter consists of several series connected newly developed single phase two transistor H-Bridge...
This In this paper, we present a new inverter topology in order to decrease the process variability influence on performances of a ring oscillator. Using FDSOI technology, we used the back-gate electrode of the transistor to symmetrize the output of a complementary inverter. This technique will reduce the variability of the inverter and the jitter (i.e. the phase noise) of the ring oscillator. Complementary...
This paper presents an on-chip common-mode cancellation circuit which increases the immunity to electromagnetic interference (EMI) of integrated CMOS operational amplifiers when EMI is injected into their inputs. The circuits have been designed in the UMC 180nm CMOS technology. Two case studies have been considered: first, the common-mode cancellation circuit has been used in a Miller amplifier and...
In this paper, a new Ultra low voltage (ULV) logic circuit based on the floating gate structure is presented. In this technique we utilized the bulks of the transistors to speed up the circuit. Using the proposed method, the speed of the circuit enhances by connecting the bulks of the evaluating and recharge devices to the clock, power supply (VDD) and input signals. The simulation results for the...
This paper presents the adaptive analog hardware implementation of a MLP (multilayer perceptron architecture) ANN (artificial neural networks) for online nonlinear system operation. Neurons are implemented by bipolar differential pairs with tangent hyperbolic activation function. A bipolar current multiplier and a linearized differential amplifier are proposed for storing and adjusting the weights...
This paper reports the analyses of two techniques for phase noise reduction in the CMOS Hartley oscillator circuit topology. Namely, the two techniques inductive degeneration and optimum current density are investigated with the objective of exploring the potential benefits in the mm-waves frequency range. The circuit sizing is carried out in 28 nm bulk CMOS technology. Overall, the analyses show...
This paper presents a feasible implementation of a single phase inverter prototype via a Highly Efficient and Reliable Inverter Concept (HERIC) topology, which is connected to the grid through a phase and frequency synchronization system by means of a Second Order Generalized Integrator — Frequency Locked Loop (SOGI-FLL). The chosen topology for the inverter design-unlike a full H-bridge (FB) inverter-incorporates...
This paper reports the analyses of two techniques for phase noise reduction in the CMOS Colpitts oscillator circuit topology. Namely, the two techniques inductive degeneration and optimum current density are investigated with the objective of exploring the potential benefits in the mm-waves frequency range. The circuit sizing is carried out in 28 nm bulk CMOS technology. Overall, the analyses show...
A new three phase three transistor voltage source inverter has recently appeared in the literature which has attractive features compared to the conventional voltage source inverter topologies. In particular, it requires a less number of costly switching devices, such as high performance transistors. This inexpensive design is considered to be advantageous in medium to high power application requiring...
This paper presents an inductorless 2.41 GHz ISM receiver, implemented in a standard 130 nm CMOS technology. The receiver consists of a feedback LNA and an IQ VCO-mixer, designed for low area and low power. The VCO-mixer is based on an IQ cross-coupled RC relaxation VCO, where two single oscillators are coupled through active loads. This topology consumes approximately 20 % less power and reduces...
This paper presents a compact transistorized lowpass filter circuit that employs global feedback to suppress the circuit's nonlinearity in the filter passband. The proposed circuit combines only 4 subthreshold-biased transistors in the filter core and 3 branches of current consumption. The proposed filter can be operated from a 1-V single supply. Circuit simulations using Cadence for 0.35-µm CMOS...
This paper proposed a novel interactive current-reused QVCO (ICR-QVCO) architecture based on capacitor-coupling self-switching sinusoidal current biasing (CSSCB) phase noise reduction technique. These interactive generated quadrature outputs have minimum phase error arising from the mismatch due to process variation and construct the better quadrature phase relationship than ones with conventional...
This paper presents characterization of low operating voltage, high speed and power efficient comparator used as a basic building block in speed optimized Analog to Digital Converters (ADC), such as flash ADC. Overall performance of any ADC in terms of speed, resolution and power consumption highly depends on the underlying comparator being used. In this paper, better structure of comparator is implemented...
This paper presents a power management circuit implementing a Synchronous Electric Charge Extraction on piezoelectric energy harvesters based on a flyback architecture. The novelty of this circuit lies in its ability to handle multiple energy harvesters operating at different frequencies and different output voltages with a single and standard flyback coupled inductor. The power harvested by the various...
In this work, new design techniques that aim to reduce power consumption of true single-phase clock-based (TSPC) prescalers is presented. The structure of divide-by-4/5 frequency divider is simplified, and its performance is compared with previous work to demonstrate the improvement. Simulation results show at least a 25% reduction of power consumption is achieved by the proposed unit. In the 32/33...
This paper present 3.1–5 GHz low noise amplifier (LNA) for UWB receivers. In this proposed circuit, cascade and cascode topology with modified input matching are designed. Proposed LNA achieves a maximum gain 22.252 dB, a noise figure 0.921–1.646 dB with a wide input matching. The power consumption is low under a 1.6-V dc power supply. The proposed UWB LNA is implemented using 0.18 μm based CMOS technology...
This paper presents a new family of Class-AB operational amplifier (OpAmp) circuits based on single-stage topologies with nonlinear current amplifiers. The proposed OpAmp architecture is mainly characterized by generating all Class-AB current in the output transistors only, exhibiting very low technology sensitivity and avoiding the need of any internal frequency compensation mechanism. Hence, this...
A linearity efficiency factor (LEF) is proposed in this paper to quantify the trade-off among linearity, bandwidth, and power consumption in designing differential pair or operational transconductance amplifier (OTA) circuits. The unitless LEF can be used to evaluate the trade-off efficiency of a circuit topology without considering the effects of input attenuation nor the bias current level when...
A noise improved Charge Sensitive Amplifier (CSA) topology for a gaseous detector readout front-ends is presented. The proposed topology is based on the traditional cascode topology with addition of a PMOS to partially cancel the channel thermal noise and the flicker noise of the CSA input transistor. A noise improvement of about 23% was obtained without increasing power consumption. Additionally,...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.