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This paper presents a 0.325-THz single-ended amplifier designed in a 28-nm FDSOI CMOS technology. The amplifier consists of four common-source gain stages and utilizes staggered-tuning along with inductive feedback (drain to gate) technique to boost up the gain over a wide frequency band. Having a total power consumption of 28 mW, the amplifier achieves a peak gain of 4.5 dB at 325 GHz. To the best...
A wide-locking range divide-by-4 static frequency divider for the mm-wave wireless applications is proposed. The capacitive-bridged inductive shunt peaking technique is investigated for widening the locking range and a compact layout area. The divider is realized in 65nm LP CMOS with a small area of 100μm × 160μm occupied. Measurement results show the present divider achieves an operation range percentage...
This paper reports a novel differential Hartley oscillator circuit topology. The circuit topology exploits the transformer coupling to enhance the effective quality factor (Q) of the LC tank and shows a potential for achieving a high spectral purity at the mm-wave frequency range. The oscillator topology has been designed for 60 GHz in 28 nm fully-depleted silicon-on-insulator (FDSOI) CMOS technology.
This paper presents a CMOS high linearity power amplifier for LTE application. We use inverter circuits and t second harmonic control to improve the linearity. This circuit will be processed with TSMC 0.18 µm technology. The simulation result shows that the circuit exhibited a power gain of 25.9 dB, an input return loss less than - 20.2/20.9dB, the PAE is about 35%/31.2% and the output power is about...
This work is devoted to development of high-voltage low drop output (LDO) voltage regulator integrated circuit (IC) for power supply units. IC is realized in 250 nm BCD (Bipolar, CMOS, DMOS) mixed technology.
This work demonstrates a fully integrated 24 GHz CMOS receiver for high gain and wireless sensor network. The receiver incorporates a low noise amplifier, double-balanced mixer and an active balun for single to differential. This mixer designs with active load to decrease power dissipation. To increase mixer gain, an inductor is added to eliminate parasitic capacitances at the load of input transistor...
A novel class-AB Flipped Voltage Follower is proposed, suitable for low-voltage low-power CMOS implementation in advanced technology nodes. Simulations have been performed using STMicroelectronics models for the 45nm technology. The Flipped Voltage Follower allows low output impedance and high linearity by means of a feedback loop. However, like the conventional common-drain voltage follower, it has...
CMOS and tunneling-FETs (TFETs) utilizing high mobility III–V channels on Si substrates is expected to be one of the promising devices for high performance and low power integrated systems in the future technology nodes, because of the enhanced carrier transport and tunneling properties. We addressed key issues to enhance the performance of III–V MOSFETs and TFETs. For the technologies enhancing the...
In the last few years, as Si electronics faces mounting difficulties to maintain its historical scaling path, transistors based on III–V compound semiconductors have emerged as a credible alternative. To get to this point, fundamental technical problems had to be solved though there are still many challenges that need to be addressed before the first non-Si CMOS technology becomes a reality. Among...
III–V integration on Si is one of the most attractive options to extend future CMOS circuits. However, direct material integration by epitaxial growth is challenging mainly due to the large lattice mismatch. Here we present a novel technique that enables InAs and GaSb nanowires to be grown on Si substrates in the same MOVPE run. By reducing the Au seed size, the nucleation of GaSb can be suppressed...
In this paper, we report that a nearly defect free In0.71Ga0.29As fin structure can be selectively grown inside oxide nano-trenches on a Ge template by using composition-graded InGaP as a buffer layer. A growth model is proposed to explain the strain energy accommodation behavior from Ge to In0.70Ga0.30P and then to In0.71Ga0.29As. This model offers a guideline for developing high quality high indium...
In the frame of the design of a low noise amplifier for W-band applications, pads, inductors, and other circuit components such as capacitors, coplanar waveguides and interconnect lines have been custom designed in a 28 nm bulk CMOS technology and simulated by means of 3D electromagnetic (EM) simulator. In particular, this paper reports the design and test of stand-alone pads, capacitor and inductor...
The cutoff frequencies and maximum frequencies of operation of short channel transistors have reached the terahertz (THz) range. In such devices, the ballistic electron transport, which was first proposed nearly 40 years ago, affects all the device characteristics - from the linear region (dominated by the so-called “ballistic mobility”) to a high field region affected by the ballistic injection....
The downscaling of the CMOS technology and the demand for low power impose new challenges on the design of mixed-mode integrated circuits, such as analog to digital converters. Consequently, the amplifier, which is one of the building blocks, has been the subject of extensive development. This paper presents recent advances in low-power technique options for the design of amplifiers within the context...
This paper presents a 0.5-3.5GHz wideband CMOS low noise amplifier (LNA) for LTE application. The LNA design is based on a common source (CS) cascade amplifier with resistive feedback that is used to do input matching and reduce the noise figure. Source follower and LC series resonances are used to do output matching. The LNA achieves the gain of 17dB ∼ 22dB, a noise figure (NF) of 2.23 ∼ 2.68 dB...
This paper presents a high-speed and high-gain dynamic residue amplifier for two-stage SAR-assisted pipeline ADC. Parametric amplification technique is incorporated in the residue amplifier to enhance the gain, in order to meet the industrial requirements of the residue amplifier of an ADC with ENOB ≥ 10.5 bits. From simulations the proposed circuit has shown a gain of 22.05 dB and a power consumption...
Design of high-speed analog-to-digital converters, high-frequency active filters and other analog signal processing systems with high demands to heir constituent units parameters, requires operational amplifiers with high dc-gain and high unity gain frequency. In developing operational amplifiers with unity gain frequency of several gigahertz and phase margin of more than 600 in the CMOS process,...
We propose a method for making THz detector antenna gain frequency dependency smooth by using conductive substrate. However, an increase of substrate conductivity decreases antenna gain even if an insulation layer is present.
In this work, the implementation of the PRESENT-80 block cipher in a 40nm CMOS technology, and its vulnerability to Side Channel Attacks Exploiting Static Power is investigated. In the last two decades, several countermeasures to thwart DPA/CPA attacks based on the exploitation of dynamic power consumption have been proposed. In particular, WDDL logic style is a gate-level countermeasure, to Power...
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