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Named Data Networking is a new data centric kind of communication network. This paper shows the study about NDN network and applies this architecture over Vehicular ad-hoc networks so that performance of network improves and communication becomes faster. At the end of simulation results are discussed in the form of packet delivery ratio, throughput, good put, routing overhead and various network parameters...
US Air Force satellite ground stations require significant manpower to operate. To improve operating efficiencies, the Air Force seeks to incorporate more automation into routine satellite operations. Interaction with autonomous systems includes not only daily operations, but also the development, maintainability, and the extensibility of such systems. This paper presents challenges to Air Force satellite...
The system architecture of a network system is of fundamental importance to the performance of computer networks. However, evaluating different architectural and algorithmic choices of network systems is usually difficult. This poster presents NetSysSim, a network system simulator implemented in SystemC. NetSysSim provides a hierarchical framework of different levels of abstraction. With SystemC's...
PCM (Phase Change Memory) as a new kind of non-volatile memory has received much attention from both academia and industry. While PCM has a number of new features, how to use PCM at memory hierarchy still remains a problem. In addition, at present PCM chips and storage devices are not available. This makes it hard to evaluate PCM-related algorithms. Thus, we design a flexible simulator named DPHSim...
Adders forms a major part in various arithmetic logical operations. Parallel Prefix Adder have been built up as the most essential and efficient circuit for binary addition. Their Particular structure and execution performance are very attractive for VLSI implementation. In these papers, we describe the design and performance of the Kogge Stone Parallel Prefix Adders and implemented using different...
Increasing demand of multiple functions in a single device or with smaller area leads to more market for devices with System on Chip (SOC). An SOC have multiple Intellectual Properties (IPs) such as Processors, memory, peripherals etcetera on a single chip. These IPs need to have an efficient bus architecture for the communication purpose which further decides the device performance. The most used...
Smart transformer (ST), which has been classified among the 10 most emergent technologies according to Massachusetts Institute of Technology (MIT), has acquired growing importance in the distribution grid. This paper presents at first the concept of ST and its advantages in the power grid. Then, the existing topologies are reviewed and compared in order to select the most performing which is the three-stage...
SoC (System on Chip) is the integration of heterogeneous components and each component can act as a bus master. Simultaneous requests from bus masters, for shared bus, pose a great challenge for on chip communication. Arbiter ease this challenge by deciding who to grant the bus for communication when simultaneous requests are made by bus masters. One of the technique that arbiter follows is the lottery...
In this paper, a PLC controlled simulation of a coupled tank system based on an existing dual-tank educational process control plant is developed. A critical analysis of the plant is carried out in order to obtain all the required parameters to setup the simulated model. Unlike the actual plant, the virtual process control model is not limited to two tanks only but may be reconfigured with ease in...
In this paper, a low latency IFFT architecture for 3rd Generation Partnership Project (3GPP) LTE is proposed. To reduce the latency, we reorder the IFFT input data. By using the reordered input data, both the latency and the memory in stage 1 are significantly reduced. Simulation results show that the latency for 2048-point IFFT is reduced about 42% compared with conventional architecture. The proposed...
This paper addresses the issue of selecting architecture of smart grid that can be used so as to test applications and uses cases related to services. Most existing architectures are based on the NIST conceptual model that defines seven high-level domains (Bulk Generation, Transmission, Distribution, Customers, Operations, Markets and Service Providers), which is not suitable with recent progress...
The predictability of execution qualities including timeliness, power consumption, and fault-tolerability is of utmost importance for the successful introduction of multi-core architectures in embedded systems requiring guarantees rather than best effort behavior. Examples are real-time and/or safety-critical parallel applications. In particular for future many-core architectures, analysis tools for...
For the better part of the last 20 years, simulation of semiconductor processes and devices had been the main focus in modeling planar CMOS transistors. The introduction of FinFETs in 2010, along with the increasing use of non-Si materials added much complexity and cost in technology development. With multiple device architectures and material options to consider, TCAD has evolved from focusing primarily...
Technology scaling has been aggressively developed during last several years and almost close to the final states. In order to cope with high density new technology, silicon based memory cell also needs to be replaced by alternate devices. Memristor is one of the promising novel elements for memory cell. This paper proposes a new memristor based hybrid memory cell, which is capable of bidirectional...
In this paper are presented the simulation results of the locomotion of MECABOT, a Modular Robotic System designed and developed in the Militar Nueva Granada University. A Webots controller file is developed starting from the equations that describe the movement of MECABOT chain architecture, considering the caterpillar and snake configurations. The variation of the parameters of the equation in the...
Designers of complex SoCs have to face the issue of tuning their design to achieve low power consumption without compromising performance. A set of complementary techniques at hardware level are able to reduce power consumption but most of these techniques impact system performance and behavior. At register transfer level, low power design flows are available. Unfortunately, equivalent design flows...
Nowadays designing a SAR Instruments is getting more and more complex. On one hand the requirements on resolution are always shrinking, leading to an increase of complexity in all the system, on the other the introduction of digital SW-reconfigurable architectures increased the number of functions and modes allocated to the same HW (mixed SAR modes, GMTI, etc.). Another important requirement that...
This paper presents the design of a multi-stage capacitive charge pump (CCP) as a gain-stage which is used in the two-stage pipelined successive approximation analog-to-digital converter (SAR ADC). The topology of multi-stage CCP and the design considerations are provided. Thereafter, the power comparison between switch capacitor (SC) integrator and multi-stage CCP is analyzed with the parameters...
Content Centric Mobile Ad-hoc NETwork (CCMANET) applies the advantages of Content Centric networking (CCN) into Mobile Ad Hoc Network(MANET) to overcome the drawbacks of low efficiency and unstable in transmission. Caching scheme is one of the key components of CCMANET. However, the caching scheme in CCMANET has not been well explored. In this paper, a novel cooperative caching scheme based on generalized...
This paper devotes to a new 5-2 compressor designed according to a new architecture with a pure Glitchless output. A considerable increase in the speed of the operation is achieved by utilizing a new truth table, fast production of signals Cout1 and Cout2, optimum tuning of the width of the utilizing transistors, and eliminating the parasitic capacitances through merging the drain of transistors....
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