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This paper presents high-power-density inverter with pulse current injection power decoupling method. In order to reduce the dc-link capacitor significantly, dc-link current is fully analyzed with double Fourier method in theory. Compared with the traditional 2nd harmonic power decoupling method, the pulse current injection method considers not only 2nd order harmonic but also the higher order harmonics...
Single phase inverters are commonly used to transfer energy from a source to the crucial appliances or emergency power system. In this study a new model based robust controller for a single phase inverter under the constraint that the output filter parameters are not exactly known is presented. The nonlinear robust controller ensures the output voltage with lowest distortion, desired amplitude and...
This paper proposed a decoupling predictive current control method for the application of traction line-side converter in high-speed railway. The method adopts a decoupled discrete-time model of the system to predict the future value of input current for all possible voltage vectors generated by the converter. Considering the calculation time, two-step prediction is taken in the scheme. The voltage...
This paper presented Proportional Resonant (PR) current control of single phase grid connected inverter for PV energy conversion to the utility grid. The synchronization mechanism is Second-Order Generalized Integrator (SOGI) phase locked loop (PLL). The PR current control is regulator in stationary reference frame and an advantage is reduce current distortion. The implemented software using Real...
Grid connected photovoltaic systems have been paid more and more attention by people. The problem of anti-islanding is a key problem that threatens the secure operation of distributed generation (DG) system, so the system must have the function of timely detecting islanding. The traditional active frequency drift (AFD) method is not fast enough, and the total harmonic distortion (THD) is large, which...
The paper proposes an original DC-AC inverter that is based on combination of buck converter with standard three-level H-bridge inverter. This inverter uses simple feed-forward control in order to obtain almost sinusoidal output currents and voltages.
Parallel inverters are often used for the interconnection of Renewable Energy Generation Systems (REGSs); however, the output efficiency using the conventional current-sharing control scheme is low at light loads. Therefore, an intelligent control scheme for output efficiency enhancement of parallel inverters is proposed in this paper. The proposed control scheme is based on the output efficiency...
This paper presents a technique to control the output voltage of series-parallel (SP) topology inductive power transfer (IPT) system by using only a primary side controller which reduces cost, size, complexity and loss compared to the conventional IPT dual-side controller. The duty cycle of the inverter output voltage is controlled by a controller located in the primary side which keeps the DC output...
Inverter-based distributed generation and related power quality problems have received much attention in recent years. Low-voltage ride-through (LVRT) is becoming mandatory in low-voltage system due to both security requirement and power-quality consideration. This paper presents a LVRT strategy for grid-connected inverter to compensate both positive-and negative-sequence reactive power to boost fundamental...
Process and manufacturing industries are using Field Oriented control (FOC) to drive the induction motor for desired performance. To perform FOC, rotor speed and stator current are sensed and fed back to the controller and the speed control of motor is achieved through an inverter connected either in stator or rotor circuit. Hence, the control system heavily depends on feedback signals and inverter...
This paper proposes a fully Digital, Analog-to-Digital Converter (FD-ADC) which is designed by using UMC's 180 nm digital CMOS technology. The advantages of the digital ADC are its simplicity and low complexity. Power dissipation is also very less compared to other ADC architectures. The FD-ADC is suitable for low power applications and where the input signal swing is small. FD-ADC also needs very...
Many existing XOR-XNOR cells suffer from nonfull-swing outputs, high power consumption and low speed issues. In this paper, a new fast, full-swing and low-power XOR-XNOR cell, is presented. Simulation results in 90-nm CMOS technology show that the proposed circuit has rail to rail outputs Also, we have gained 11%–51%, 2%–19% and 18%–52% improvement in delay, power consumption and power-delay product...
This paper presents a metastability detection circuit to improve the bit-error-rate (BER) of analog-to-digital converters (ADCs) which use the asynchronous operation. In comparison with conventional metastability detectors (MDETs), the proposed replica-type MDET is more helpful to improve the BER with better immunity to process, voltage, and temperature (PVT) variations. The proposed MDET can effectively...
This paper firstly introduces the principles of SPWM (space vector pulse width modulation) and SVPWM (sinusoidal pulse width modulation), and then builds PMSM (permanent magnet synchronous motor) control system simulation models based on SPWM and SVPWM in MATLAB/Simulink environment. Finally, by comparing the simulation results of the two models, we got the advantages and disadvantages of SPWM and...
RAM decoders were simulated on base the bulk CMOS 28-nm design rule. The result of a single nuclear particle impact on a MOS logical gate is a noise pulse as a single-event transient. The internal error decoder gives the main contribution to a noise sensibility of a RAM decoder. The combinational logic of error decoder can prevent all noise pulse propagating through NAND and NOR gates for the output...
Multiport CMOS cell with the soft-error immunity based on DICE which is divided into two spaced groups of transistors each of them consisting of four transistors. The larger the distance between these two CMOS transistor groups, a multiport SRAM is more hardened to single event upsets. The result of a single nuclear particle strike only on the one transistor group of a DICE trigger is a single-event...
This paper presents a novel control scheme for seven levels diode clamped multilevel inverter (DCMLI) topology based shunt hybrid active power filter which can compensate both dynamic reactive power and current harmonics in three phase three wire medium voltage distribution power systems as against many literatures that compensate fixed reactive power. It is on account of this novel control method,...
The speed of any processor largely depends on the cache memory that it incorporates and the cache memory is predominantly made up of Static Random Access Memory (SRAM) cells. Therefore, with the technology shrinking every year, it is becoming essential to improve its reliability. This paper presents a qualitative analysis of a 6T Static Random Access Memory (SRAM) cell when it has been induced with...
This paper presents a novel generalized topology of a multilevel inverter. The proposed topology is obtained by extending the developed H-bridge topology. The proposed topology is competent to generate the optimum number of output voltage levels by using minimum number of dc voltage sources. The topology offers reduced value of voltage stress on semiconductor power switches. Utilization of dc voltage...
To take out a variable frequency variable amplitude output voltage a new single-phase H-bridge multilevel inverter (MLI) topology is constructed through VFISCPWM modulated semi-cross switched voltage sources along with a hybrid pulse width modulation (PWM) strategy. The principle avoids a shrewd attitude to employ PWM approach only for a meticulous H bridge that serves to produce the desired level...
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