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This paper presents the simulation, construction, and validation of a new topology of a DC/DC Buck power converter-DC motor system. The main objective is to achieve forwards and backwards rotation on the DC motor shaft. For this purpose a full-bridge converter is installed between the DC/DC Buck power converter and the DC motor. Also, as a result of applying Kirchhoff's current and voltage laws and...
VLSI technology is an emerging field in the current technological scenario due to its advancements in fields of systems architecture, analog and digital logic and adders are the basic building blocks in digital integrated circuit based designs. The existing Ripple Carry Adder (RCA) has the most compact design but takes longer computation time. The time critical applications use Carry Look-ahead Adder...
A high speed and power efficient synchronous counter is proposed using True Single-Phase Clock (TSPC) based Toggle Flip-Flop (TFF) with the Extended True Single-Phase Clock (E-TSPC) based combinational logic embedded in it. The principle of realizing both synchronous up and down counter at both positive and negative edges using these flip-flops are discussed. Also gray counter is accomplished using...
In this paper, low voltage low power highly linear operational transconductance amplifier (OTA) using source-degeneration technique is presented. Source-degeneration techniques improve the bias current of the input differential pair when large signals are applied, thus, increasing circuit dynamic characteristics without affecting stand-by dissipation. The OTA is designed to operate with a ±0.55V supply...
Sigma-Delta Analog-to-Digital converter (ADC), is widely used in portable electronic products. An operational transconductance amplifier (OTA) is one of the most important components of this ADC. This paper reports a new design of low power fully differential OTA. In this design authors have used adaptive biasing technique and DC gain enhancement technique for improving design parameters as compared...
This paper, presents a new design for 1-bit full adder cell using hybrid-CMOS logic style. The new full adder is based on a novel XOR-XNOR circuit that generates XOR and XNOR full-swing outputs simultaneously and outperforms its best counterpart showing 43% improvement in power-delay product (PDP). The proposed full adder provides full-swing output with good driving capability and it is a proper choice...
In this paper, a simple filter topology that can be used to implement first-order MOS-only allpass filter is proposed. The proposed MOS-only allpass filter offers inherently very accurate magnitude and phase characteristics at very high frequencies. However, MOS-only active filter suffers from an inherent low frequency limitation. In order to address this issue, the modification technique allowing...
In this paper, a new coupling circuit is presented. This circuit uses a new method of subthreshold region biasing to decrease the value of coupling capacitor. In proposed circuit the Coupling capacitor is decreased about 98% in comparison with the ordinary capacitive coupling circuit. In addition, the proposed coupling circuit achieves higher linearity. The performance evaluation of proposed circuit...
In order to drive both positive and negative directions in the shaft of a DC motor connected to a DC/DC Buck power electronic converter, this paper presents a new topology of the DC/DC Buck power electronic converter-DC motor system. To this end, a full-bridge converter is placed between the Buck converter and the DC motor. The deduction of the mathematical model step-by-step, from applying Kirchhoff's...
One transistor one resistor (1T1R) structure can be used to suppress the sneak current in RRAM array. In this paper, a 16Mb 1T1R RRAM chip is proposed. The 130 nm HH-Grace process is used as the FEOL of the chip. A HfOx/CMO based RRAM stack will be fabricated using back end process. The chip mainly contains four blocks: the RRAM array, the analog power block, the control logic block and the pad ring...
We present modeling and simulations of graphene coplanar waveguide (GCPW) under the frequency up to 50 GHz. Our simulation results show that the dimensions of GCPW greatly influence its insertion loss. In addition, different graphene layer numbers and structures of graphene-metal contact were also considered. We show that the usage of few-layer graphene and end-contact structure is able to decrease...
In this paper, a novel architecture for charging mode controller of Li-Ion battery charger is proposed. It is design to generate stable control signals even when noise level reaches several tens of millivolts. The trickle current is as low as 200mA enabling longer life cycle for Li-Ion battery. The large current reaches 1A without any impact on trickle current offering a faster charging time for Li-Ion...
Basic structure of latch-type SRAM sense amplifier is analyzed and advantages and disadvantages are compared in this paper, then an improved latch-type SRAM sense amplifier is presented. On this basis, a new sense amplifier is proposed, which can access data fast for low voltage and low power SRAM application. The simulation results show that this sense amplifier has advantage over the conventional...
This paper deals with the analysis of losses, calculations for switched reluctance motor (SRM) power, converter. Switching and conduction losses are calculated by, analytical methods and they are compared with simulations results, for several values of motor speeds and torques. Losses are, calculated for one phase in steady state during its conduction, interval. Converter consists of real power modules...
A framework for the simulation of nanosecond laser annealing of structures found in 3D sequential integration is presented. The framework includes a finite difference frequency domain Maxwell solver and a Poisson solver for the thermal diffusion. Simple applications illustrate the advantages, expected difficulties and optimization levers of this annealing technique.
A non-coherent 10Msps Ultra-Wideband (UWB) receiver using 3.1–5GHz pulse position modulation (PPM) signaling is implemented in a 65 nm CMOS process. The receiver is mainly comprised of low noise amplifier (LNA), squarer, integrator and comparator. All RF and baseband circuits operate at 0.5-V power supply. The chip area is 1.1mm×1.0mm. Total power dissipation is 7.44mW and 0.8nJ/bit can be achieved...
The author's career has coincided with the development of numerical simulation into an essential component of semiconductor device technology research and development. We now have a sophisticated suite of simulation capabilities along with new challenges for 21st Century electronics. This talk presents a short history of the field and a description of the current state of the art, but it concentrates...
In todays scientific scenario the need for reducing power dissipation for high end devices like Analog to Digital Converters, operational amplifiers is of utmost importance. One of the important contributors to power dissipation is leakage current. In this paper we propose a charge sharing lector comparator which significantly reduces leakage current. The circuit is primarily based on the LECTOR technique...
The common way of characterizing the metastability properties of a circuit is by its metastability resolution constant tau and the aperture window. This approach is based on a model that represents the storage cell as a pair of crosscoupled inverters, each of which is, in turn, modeled by a constant-gain amplifier with a first-order low-pass filter at the output. The former reflects the inverter's...
This study presents a novel SRAM architecture focused on minimizing area utilization for sub- and near-threshold operation in ultra-low power applications. This new architecture utilizes a modified 6T SRAM cell, introduces horizontal bit-lines, mitigates half-select disturb, and supports bit-interleaving. The proposed design's stability was thoroughly tested in the presence of process, temperature,...
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