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This paper presents a locking-accelerated DPLL based on multi-output bang-bang phase detector (MOBBPD) with reused most significant bits (MSBs). The bang-bang structure has simple implementation by eliminating the sensitive time-to-digital converter (TDC), while MOBBPD allows for reduced loop locking-time due to the multi-output. To further accelerate the loop locking, a scheme of reusing the MSBs...
In this paper, a 1.8-V 3-bit quadruple-sampling delta-sigma modulator for audio application is presented. To performance high-resolution and low-cost modulator, a single opamp is used to complete the integration with four phases. Since the phase difference between any two succeeding clocks is 90 degrees, the sampling rate will be four times of clock frequency. The effective integration time can also...
This paper proposes a pipelined time stretching technique for high throughput counter-based time-to-digital converters (TDC). Time stretching technique is used to increase the resolution of counter-based TDCs, yet it carries an inherent weakness of having a long conversion time due to the stretching phase. Without significant increment of chip area, the proposed pipelined time stretching method is...
This paper proposes a low power 10-bit single-slope analog-to-digital converter (SS-ADC) for CMOS image sensors (CISs) with a column-parallel readout structure. The power consumption of the proposed SS-ADC is reduced by using a power gating scheme for the comparator and multi-clocks having different frequencies. The proposed SS-ADC was designed using a 0.13μm CIS process technology. The simulation...
Atomic multicast is a group communication primitive that allows disseminating messages to multiple distributed processes with strong ordering properties. As such, atomic multicast is a widely-employed tool to build large-scale systems, in particular when data is geo-distributed and/or replicated across multiple locations. However, all the most efficient atomic multicast algorithms suffer from a convoy...
We present in this paper a method and tool for the verification of causal and temporal properties of embedded systems, by analyzing the trace streams resulting from virtual prototypes that combines simulated hardware and embedded software. The proposed method makes it possible to analyze different kinds of properties without rebuilding the simulation models. Logical clocks are used to identify relevant...
To cope with data collision problem in consensus synchronization algorithm caused by utilizing pseudo-periodic broadcast method, this paper presents a novel gossip averaging based clock synchronization protocol, which combines the a synchronism of rumor communication and the robustness of neighbor averaging. We design a randomized link-activated based relative skew estimation strategy, which realizes...
As distributed systems such as automotive, medical, manufacturing automation become larger and more complex, it is difficult to test these systems. Also, the synchronization of distributed applications make the testing more difficult. In the Software-in-the-Loop (SiL) simulation, a synchronization method among clock of applications is provided for virtual hardware devices and environment. A typical...
Designers of complex SoCs have to face the issue of tuning their design to achieve low power consumption without compromising performance. A set of complementary techniques at hardware level are able to reduce power consumption but most of these techniques impact system performance and behavior. At register transfer level, low power design flows are available. Unfortunately, equivalent design flows...
Over many years, the technology of circuit refinement has achieved a tremendous large-scale integration, so that VLSI systems such as many-core VLSI processor have emerged. However, in the huge VLSI systems, various problems such as many communication problems of the VLSI network, clock synchronization of the entire system, and verification of concurrent processing, must be solved in order to realize...
This paper presents a scalable time optimized online test solution that addresses short faults in interconnects of an on-chip network (NoC) and observes the deep impact of these faults on NoC performance at large traffics.
Xilinx FPGA design tools Vivado support project based mode and none project mode, the project based mode is used by most of the designs with powerful graphical interface IDE, but none project mode also has its unique advantages and magical effect, this paper presents a method of post-synthesis simulation based on none project mode of Vivado, which can find errors early, such as the simulation result...
In this paper, we design and implement the Clock and Data-Recovery (CDR) with Serializer/Deserializer (SerDes) on Spartan SP605 supports a data-rate up-to 3.2 Gbps with locking time less-than 5×10−7 s, and bit-error rate less-than 10−10.
Digital discrete-time implementations of non-Foster circuit elements offer an alternative approach to the design of devices such as negative capacitors and negative inductors. However, practical implementations of high-speed digital non-Foster circuits are affected by latency and noise, where latency can arise from analog-to-digital conversion time and computation time. Thus, the present work explores...
This paper presents a comparable study of the locking characteristics of phase-locked loops (PLLs) with an integrating bang-bang phase detector with that of PLLs with an Alexander full-rate bang-bang phase detector. Both periodic and single-event data transients are used to investigate the lock performance of two PLLs with identical configuration and components but different phase detectors. Simulation...
In this paper a digitally-assisted foreground-liked calibration technique is proposed for offset cancellation of the residue amplifiers in high-resolution analog-to-digital converters. Two amplifiers are used while are in turn corrected for offset error. When the first amplifier participates in residue amplification the second one is calibrated to be substituted in the main data path. Two analog comparators...
Increasing demand of multimedia functions in mobile influenced systems provides limitations to battery usage in terms of power. To overcome this problem SLIMbus is designed by MIPI alliance which gives higher bus bandwidth by supporting more number of data channels, supports clock gear mechanism that gives less power consumption in hand held devices by changing the clock frequency dynamically. SLIMbus...
This paper presents a discrete time fully differential CMOS signal conditioning circuit for acquisition of biosignals. It is realized using switched capacitors (SC), which provides reconfigurability, high precision, high CMRR and low sensitivity to temperature and process variations. However, the SC circuit suffers from various errors like charge injection and clock feedthrough which have an impact...
A large number of computer applications(like Computer Graphics, Control Systems, Modeling System, Simulators etc.) needed floating point arithmetic. However, most of the presently available methods are slow and inefficient because of sequential design however the recent development in the field of programmable logic devices such as FPLA and CPLD opens the new area of parallel and high speed floating...
This paper deals with hybrid Digital Pulse Width Modulator (DPWM) architecture to generate a variable duty cycle pulse to control the switch of power converters. The proposed architecture highly utilizes the logic blocks present in Field Programmable Array (FPGA) to derive the variable duty cycle Pulse Width Modulation (PWM) pulses. This architecture uses the clock multiplying capability of on chip...
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