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For pursuing the high speed information transmission, the design and research of the high speed SerDes circuit are actively developing now. Due to the requirements for long transmission path, intensive equalization and high speed transmission circuit testing function, two high speed SerDes circuits are designed and fabricated based on 130nm SiGe BiCMOS technology. One is for the research of the equalization...
The paper offers the simple voltage source multilevel inverter space vector PWM algorithm (based on the oblique-angled coordinates of two delta voltages) with the optimum three-segment non-symmetric vectors switching sequence variant providing the instantaneous output voltage quarter-wave symmetry. The comparisons with the five-segment variant by the voltage waveforms, spectra and THD are performed...
In this work, we investigate information spreading in multiplex networks, adopting the gossip (random-walk) based model. Two key features of multiplex networks allow potentially much faster information spreading: availability of multiple channels and communication actions for each user, and more choices on neighbor contacting. As a first work in this area, we explore the impact of layer number, layer...
The problem of faults is growing exponentially due to embedded memory area on-chip is increasing and memory density is growing. There are two types of memory single port and multiported comparing these two memories multiported memory have ability to support more efficient execution of operation and high speed performance. Built-in self test is used to detect and repair the faults in multiported memory...
This paper proposes simple simulation modeling method of Electromagnetic Interference (EMI) and predicting potential risk of EMI radiation by specific noise source focused on Printed Circuit Board (PCB). Electromagnetic Simulation (EM) is commonly used to accurately determine the root cause of EMI problems on a PCB. The drawback of EM simulation is that it sometimes requires prohibitively large computing...
This paper studies the content of logistics planning simulation. It designs the process and procedure of planning simulation from three aspects, such as discrete event, service object and logistics field work. Discrete event simulation algorithm and service object simulation algorithm are presented. Then it proposes to reconstruct the logistics business process and optimize the existing logistics...
A precise timing system that consists of two delay-locked loops (DLLs) is proposed to align the sampling phases of the time-interleaved ADC (TI-ADC) with the front-end Sample and Hold (S/H) clock. DLL1 using bang-bang phase detector (PD) handles the 1 GHz system clock and DLL2 produces 32 phases to generate the non-overlapped clock in the followed 4 pipeline ADCs. A new self-calibration scheme in...
Inter-Integrated Circuit (I2C) plays an important role as an interface in communication between devices. EEPROMS, ADC, DAC and RTC require an interface for communication and I2C is used as an interface between them. The RTL behavior of the I2C Master Controller is verified using System Verilog and its verification is carried out in Mentor Graphics tool. The functionality of the design is verified...
This paper presents a biopotential acquisition unit with an instrumentation amplifier and analog-to-information converter for wearable health monitoring applications. The instrumentation amplifier defines the quality of the acquired biopotential signals. At the heart of the system is an Analog to Information Converter (AIC) to enables the random under-sampling operation. AIC is used to digitize the...
The new generations of aircraft embark, growingly, avionics systems and functions to increase passengers' security and comfort. Therefore, a huge increase in data traffic is generated. Higher rates with more interconnections become necessary. However, Conventional avionics communications busses cannot meet these new needs. They are prompting avionics manufacturers (Airbus and Boeing) to install on...
In this paper typical approaches to mitigate single event effects using spatial redundancy were reviewed. The specificity of receivers input tracts were described. The low power techniques as the clock gating have a significant impact on the work conditions of a digital receiver. A novel modification was proposed for storage cells which are insensitive to radiation-induced single event upsets such...
With the rapid development of urban rail transit, the velocity measurement and location technology of train has become one of the key technologies of the automatic operation control system of the train. To realize the interval of the train and safety-control of train velocity, we must first timely acquire the operation velocity and the current location of the train. The accuracy of velocity-measurement...
In this paper a structure for high-speed incrementing/decrementing accumulator is proposed based on even and odd unit cells. Step of accumulation can be chosen among ±2n levels where n = 0, 1, 2, 3, … through a control digital word. A 10-bit accumulator is divided into two 5-bit accumulators where each one is realized in carry-ripple adder/subtractor structure. Basic cells are highly improved in number...
This paper presents a low-power on-chip RC oscillator with compensation for temperature and supply voltage variation. This circuit is based on a conventional on-chip oscillator, with only a capacitor and a comparator to avoid mismatch. Multiple current sources flow through the same resistor to generate a reference voltage. This is complemented with the dynamic element matching technique to reduce...
Clock data recovery (CDR) circuit is an essential component for serial data communication. S/PDIF which is one of data coding is used. The CDR based on PLL recovers clock and data of 2.8224 ∼ 24.576MHz and was designed with the frequency detector (FD) to detect the frequency by using the preamble. The PLL, frequency detector (FD) and the reset circuits were used to design the refernceless CDR based...
In this paper, a low latency IFFT architecture for 3rd Generation Partnership Project (3GPP) LTE is proposed. To reduce the latency, we reorder the IFFT input data. By using the reordered input data, both the latency and the memory in stage 1 are significantly reduced. Simulation results show that the latency for 2048-point IFFT is reduced about 42% compared with conventional architecture. The proposed...
Waveform of the pulse from detectors carry the maximum possible information, and the high demands of fast waveform digitizing led to the development of switched capacitor arrays (SCAs). A prototype of two channels transient waveform digitization ASIC has been designed and fabricated in global foundry 0.18 urn CMOS process. Each channel employs a SCA structure of 128 samples deep, and the high speed...
This paper presents a directly triggered asynchronous successive approximation register (SAR) logic with variable delay unit. With the help of the designed logic, the CDAC can be settled directly by the comparator result that avoids long propagation delay as conventional SAR logic does. Moreover, a variable delay unit is designed which provides more settling time to the last several bits to get more...
Ground Battlefield Simulation (GBS) is carried out to avoid actual movement/usage of resources (manpower, vehicles and weapons). GBS usually stretches from hours, days to months, depending upon the Scenario visualized/exercised. Though we have already saved upon resources, time is still an important factor that we are always short of. Simulating a Ground Battlefield scenario of a few hours at normal...
Digital PID control is a practical alternative for industrial production process, but it is not adequate for high speed processing. Using the modular method and the single process state machine design method, a hardware design scheme based on FPGA is presented to realize incremental digital PID controller. And the FPGA system is designed, compiled and simulated in QuartusII environment. The controller,...
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