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Testing for small delay defects (SDDs) is important due to their dominance in recent technology nodes. Unfortunately, all the SDD test quality metrics in the literature limit their assessment to the size of the delay defect tested under at-speed or slower clocks, which makes their results misleading under special cases such as faster-than-at-speed testing. Moreover, those metrics are inadequate for...
L-3 Communications Electron Technologies Inc., (L-3 ETI), has completed space-flight qualification for a 150–300-watt K-band traveling-wave tube amplifier (TWTA) capable of over 3 GHz instantaneous bandwidth and being configurable for either conduction cooling or direct radiating. This paper will discuss the TWTA performance, manufacturing and flight qualification test results.
Nowadays, to achieve better performance, some "smart device" needs an ultra accurate analog signal source to trim/calibrate its internal circuit during mass production which is very challenging for current ATE vendors. To design such a highly accurate signal source, it requires lots of engineering time especially in system architecture optimization, system noise estimation and performance...
With the continuous shrinking of technology nodes, lithography hotspot detection and elimination in the physical verification phase is of great value. Recently machine learning and pattern matching based methods have been extensively studied to overcome runtime overhead problem of expensive full-chip lithography simulation. However, there is still much room for improvement in terms of accuracy and...
In the nanometer era where the operating speed of a chip decides its price, design companies rely on high-qualty speed binning approaches to maxmizie their profits. The conventional speed binning approach is legacy (i.e. structural) since functional tests are too expensive to derive. Besides legacy and functional tests, recent studies tried to apply the notion of delay testing for deriving speed-binning...
In today's fast growing and increasing complex world of VLSI circuits, test quality has significant effect on the quality of the product. A malfunctioning circuit is a result of design flaw, manufacturing defects or both. Testing is used as a measure to estimate the quality of design. High quality testing minimizes defect-per-million (DPM) and thus can significantly reduce manufacturing costs and...
This paper investigates representation of a multivariable linear time-invariant system by matrix fraction descriptions (MFD). The main theoretical results in our recent paper [1] have resolved several long-standing issues of MFD models, including uniqueness of MFD pairs fA(z) B(z)g for a given impulse response of the system, complete characterization of the orders of all possible MFDs of a given system,...
This paper presents an approach to aid teaching of Digital Logic and Computer Organization through generation of dynamic assignment statements along with development of automatic generic checkers for those assignments using the COLDVL virtual laboratory package. Dynamically generated problem statements ensure a fairly large set of, distinct problems. The automated generic checkers allow the solutions...
With process scaling and the adoption of post-CMOS technologies, permanent faults are becoming a fundamental problem. Circuits containing defects are either discarded (reducing yield) or partially disabled (reducing performance). In this paper, we propose a general approach using supervised and discriminative learning techniques to compensate for the effect of permanent faults on a circuit's output...
This demonstration centered around the, design, simulation and verification of the ‘Ripple Sort Algorithm and circuit implementation’ [1] using VHDL synthesizable testbench verification techniques. The purpose of this demonstration is to show; the advantages and benefits for using synthesizable testbench verification techniques by means of inexpensive off-the-shelf tools. How an ASIC/FPGA design can...
In recent years, various high-level test synthesis methods for data paths have been proposed for the improvement in design productivity and test cost reduction. Most of the approaches assume that controllers and data paths are isolated from each other, and hence the hardware overhead becomes large. On the other hand, the approach without separation of a controller and a data path usually decreases...
DC circuit breakers are essential components in the protection of multi-terminal and meshed DC grids. So far, no practical application of HVDC circuit breakers is known and intense research is being carried out regarding various concepts, practical realization and ultimately testing of such devices. In the present contribution, several breaker concepts, based on the hybrid method of DC fault current...
Power distribution equipment is the backbone of any Industrial process infrastructure. Safety and reliability are the two most important criteria in the proper functioning of the power distribution system. Low voltage switchgear is an important part of power distribution. Minimizing arcing faults in the switchgear is of utmost importance to enable a safe environment. Arcing faults increase the temperatures...
Diagnosis of each failed part requires the failed data captured on the test equipment. However, due to memory limitations on the tester, one often cannot store all the failed data for every chip tested. Consequently, truncated failure logs are used instead of complete logs for each part. Such truncation of the failure logs can result in very long turn-around times for diagnosis because important failure...
Defects in TSVs due to fabrication steps decrease the yield and reliability of 3D stacked ICs, hence these defects need to be screened early in the manufacturing flow. We propose a non-invasive method for pre-bond TSV test and diagnosis that does not require TSV probing. We use open TSVs as capacitive loads of their driving gates and measure the propagation delay by means of ring oscillators. Defects...
Kayal has recently introduced the method of shifted partial derivatives as a way to give the first exponential lower bound for computing an explicit polynomial as a sum of powers of constant-degree polynomials. This method has garnered further attention because of the work of Gupta, Kamath, Kayal and Saptharishi who used this method to obtain lower bounds that approach the "chasm at depth-4"...
Design-for-testability (DFT) reduces the test complexity of sequential register-transfer-level (RTL) circuits. Only enhanced scan technique from the scan based approaches guarantee two-pattern testability with a large area and test time overhead. This paper proposes a path delay DFT technique for functional RTL circuits. Data paths are modified into hierarchical single-port-change (SPC) two-pattern...
This paper proposes a process of determining geometrical configurations to simulating the flow in designing sub-sonic open circuit wind tunnels. Design rules that are based on empirical results and Computational Fluid Dynamics (CFD) model are integrated as a Low-Speed Wind Tunnel Design Tool. The tool allows users to undertake the automatic calculation through wind tunnel designed requirements to...
Coordination is playing a key role in complex cyberphysicalsystems (CPSs). The complexity and importance of coordination models and languages for CPSs necessarily lead to a higher relevance of testing during development of CPSs. Model-based testing is a promising technology to test the conformance or non-conformance relation between the implementation-under-test (IUT) and its specification. In this...
Hardware-In-the-Loop (HIL) testing using real-time simulation allows system designers to lower risks associated with system integration of new technology. Controller HIL (CHIL) is used here to verify the controller platform of a 15 MW amplifier that will be used as a grid simulator in Power HIL (PHIL) configuration. This allows elements of a smart electrical distribution system to be tested in an...
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