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This paper describes the design of a PLL-based and integer-N quotient frequency synthesizer (QFS) suitable for V, E and W multiband mm-wave applications. The complementary NMOS and PMOS dual-injection structure with independent gate bias and co-tuning technology are adopted to improve injection efficiency and extend frequency locking range of ILFD. The ameliorated pseudo-differential cascode structure...
A new method of high level test generation based on the concept of test groups to prove the correctness of a part of system functionality is proposed. High-level faults of any multiplicity are assumed to be present in the system, however, there will be no need to enumerate them. Unlike the known approaches, we do not target the faults as test objectives. The goal of using the test groups is to extend...
Several EDA tools automate the debug process1,2 or part of the debug process3,4. The result is less manual work and bugs are fixed faster5. However, the actual process of fixing the bugs and committing the fixes to the revision control system is still a manual process. In this paper we explore how to automate that last step: automate bug fixing. First we discuss how the automatic bug fix flow should...
Existing functional Trojan detection methodologies assume Trojans violate the design specification under carefully crafted rare triggering conditions. We present a new type of Trojan that leaks secret information from the design by only modifying unspecified functionality, meaning the Trojan is no longer restricted to being active only under rare conditions. We provide a method based on mutation testing...
Excessive power consumption during testing has been one of the most important issues from the exponential advance in semiconductor manufacturing technology. In this paper, a scan segment skip technique is proposed to reduce power consumption by skipping segments that don't need scan in/out processes. Also, a new pattern merge algorithm is proposed for maximizing power reduction ratio. Experimental...
IR-drop induced by launch switching activity (LSA) in capture mode during at-speed scan testing increases delay along not only logic paths (LPs) but also clock paths (Cps). Excessive extra delay along LPs compromises test yields due to false capture failures, while excessive extra delay along CPs compromises test quality due to test clock stretch. This paper is the first to mitigate the impact of...
The increasing power consumption during the chip testing process has become the bottleneck of chip production and testing for micro-nano VLSI circuits. Numerous low power design-for-testability (DfT) techniques have been proposed to deal with the test power problem, and segmented scan method was shown to be an efficient solution. We propose a new poweraware scan segment architecture, which can accurately...
In this paper we consider detection of faults in CMOS cells that are more complex than primitive gates. We derive a single set of tests based on functional description of the cells. The tests derived, if applied, detect multiple stuck-at faults, multiple transistor stuck-open faults, cross wire open faults, delay faults and bridging faults between inputs of the cell, in any implementation of the cell...
‘Flipping the Classroom’ is a well-known effective educational approach which can produce significant learning gains. Students are doing the preliminary cognitive work to gain knowledge and comprehension outside of class, then focusing on the advanced cognitive work on application, analysis, synthesis, and evaluation in class. However, practically its application is quite challenging due to the limited...
TSVs can be fabricated with pitch of only tens of μm, and smaller. They can be densely distributed as inter-die interconnect in 3D ICs. However, the huge mismatch between the probe technology, such as the pitch of probe head and the capacity of probe card, and the TSV fabrication technology leads to an insufficient probe on TSV tips. In this paper, we present a novel TSV probing technique that can...
In this work we present a novel fault-tolerant circuits design method. It combines time and area redundancy to achieve error-correction abilities similar to a triple-modular redundancy (TMR) and the area-overhead close to a duplex system. New logic gates design allowing a complete stuck-at fault testability will be presented. Our method allows to test combinational parts of the circuit using a universal...
Commercial gallium nitride (GaN) high-electron mobility transistors (HEMTs) are tested in the radio frequency (RF) spectrum at heavy ion facilities to explore space environment stresses on these emerging technologies. Findings indicate that gate leakage degradation is a key parameter to consider when selecting devices. Variations in the manufacturing process may drive product selection for use in...
Hydro-Quebec has started a Smart Grid project in 2003. Among the different telecommunication technologies, Hydro-Quebec has chosen the Public Telephone Infrastructure for financial reasons. However, telecommunication metallic lines are potentially exposed to voltage induction caused by current circulating on nearby electric lines. Voltage-limiting devices are used to protect communications equipment...
Two 32nm SOI single-event upset test chips have been irradiated at LBNL and TAMU heavy ion test facilities. The test chips include unhardened and RHBD designs such as DICE, LEAP DICE, and stacking devices. SEU cross-section data are presented for the hardened and unhardened flip-flop designs across test facility, beam tune, angle of incidence, and clock frequency.
Heavy ion single-event effect (SEE) measurements on Xilinx Zynq-7000 are reported. Heavy ion susceptibility to Single-Event latchup (SEL), single event upsets (SEUs) of BRAM, configuration bits of FPGA and on chip memory (OCM) of the processor were investigated.
Parallel connected Active Front End (AFE) voltage converters are widely employed in high-power grid interfaces for renewable energy applications. With parallel connected two level power converters, the power rating of the system can be easily increased with higher stability and less control efforts than multilevel power converter based solutions. However, due to unmatched modules, unbalanced currents...
Protection from over-current situations and the resulting risk of device failure is a requirement when testing limited-run, experimental modules. This paper demonstrates a fast, configurable, and consistent means for protecting against over-current conditions during Clamped Inductive Load (CIL) testing of 10 kV SiC MOSFET modules. This protection circuit offers the user a convenient method of selecting...
For the reliability considerations, a 60-V power p-channel LDMOS transistor co-designed with none-OD zone in the bulk end by a 0.25-μm process will be evaluated in this paper. From the experimental data found that as the none-OD zones inserting, meanwhile the none-OD zone percentage was increased, the anti-ESD capability will be strengthened too, i.e. its It2 value is improved by using this manner...
QCA (Quantum-dot Cellular Automata) is the promising future nanotechnology for computing. In QCA, the cells must be aligned properly at nano scales for proper functioning. Defects may occur in synthesis and deposition phase. So the defect analyses and testing cannot be ignored. This paper presents a survey on QCA basics, defect characterization and various testing aspects of QCA.
Reliability of power electronic systems is of paramount importance in industrial, commercial, aerospace, and military applications. Faults in power converters are classified as short circuit faults, open circuit faults, and degradation faults. Short circuits (S-C) in most cases cause an overcurrent condition that is readily detected and acted upon by standard protection systems. However, open circuit...
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