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This paper presents an optimized architecture for a first-one detector (FOD) using a uniform partition decoding scheme based on the statistical distribution of the input code words. The proposed architecture uses a conventional method to optimize the Boolean expression of the input code words. Experimental results show that the proposed approach covers only 58 gates in a 0.25 m CMOS technology. Based...
The Stored Unibit Transfer (SUT) encoding has been recently proposed as a redundant high-radix encoding for each of the channels of a Residue Number System (RNS) that can improve the efficiency of Binary Signed Digit (BSD)-encoded RNS. However, a residue-to-binary (reverse) converter for it has not yet been reported in the open literature. In this paper we introduce SUT-RNS reverse converters for...
Test points provide additional control to design logic and can improve circuit testability. Traditionally, test points are activated by a global test enable signal, and routing the signal to the test points can be costly. To address this problem, we propose a new test point structure that utilizes controllability don't-cares to generate local test point activation signals. To support the structure,...
The 3N encoding process can simply add the input data N to its 1-bit left-shifted value 2N using the combinational digital circuits, such as ripple carry adder (RCA) or carry look-ahead adder (CLA). This paper presents an efficient algorithm and its hardware implementation. Results show that the proposed RCA-like 16-bit encoder achieves 25% less in hardware cost and 50% faster in speed performance...
The explosion of data consumption has led to a renewed interest in byte caching. With studies showing potential reductions in network traffic of 50%, this fine grained caching technique looks like a very good and attractive solution for mobile wireless operators. However, properties of wireless networks actually present new challenges. We first show that a single packet loss, re-ordering or corruption...
We propose and simulate a code-division-multiplexing (CDM) over-fiber passive optical network (COF-PON) system using novel logical operation coding to eliminate multiple access interference (MAI). In this COF-PON system, CDM is accomplished in the frequency domain. At the transmitter, data from each user is encoded with a group of selected subcarriers, and then fed through the fiber. Non-linear effect...
This paper proposes a high throughput context adaptive variable length coding (CAVLC) hardware design for high bit rate HEVC standard. The proposed design adopts a multi-coefficient encoding architecture with the input-parallel information-cascade method to solve the data dependency while attain high throughput. The final implementation with 90nm CMOS technology can process at least 3.2 coefficients...
This paper presents a fine-grain pipelined asynchronous circuit that uses a mixture of dual-rail and single-rail logic. Dual-rail logic is limited to construct a stable critical path. Based on this critical path, the handshake control circuit is greatly simplified, which improves the performance of speed and power consumption. On the other hand, non-critical paths are composed of single-rail logic...
This paper proposes a new watermarking scheme for intellectual property (IP) protection of sequential circuits. The method embeds the watermark by encoding the state variables as opposed to modifying the states and edges of state-transition graph (STG) in conventional finite state machine (FSM) watermarking schemes. It has the merits of being applicable to gate-level implementation of sequential circuit...
A pipelined hardware implementation is provided for a fast binary image fractal coding. The related algorithm suggests each range segment, R segment, is classified into three groups of absolutely black, absolutely white, and non-monochrome. For absolutely black and absolutely white R blocks, which are very probable in binary images, the required storage and computation has low cost. For non-monochrome...
External memory bandwidth is the most critical issue of video coding for high performance or low power concerns. To solve this issue, this paper presents a simple yet efficient lossless embedded compression engine. The engine uses adaptive differential patterns to reduce the data redundancy and encodes the residuals with simple Golomb Rice coding. For data that cannot be compressed, the engine adopts...
This work aims at investigating the automatic recognition of speaker role in meeting conversations from the AMI corpus. Two types of roles are considered: formal roles, fixed over the meeting duration and recognized at recording level, and social roles related to the way participants interact between themselves, recognized at speaker turn level. Various structural, lexical and prosodic features as...
The Stochastic Computational Element (SCE) uses streams of random bits (stochastic bits streams) to perform computation with conventional digital logic gates. It can guarantee reliable computation using unreliable devices. In stochastic computing, the linear Finite State Machine (FSM) can be used to implement some sophisticated functions, such as the exponentiation and tanh functions, more efficiently...
SAT solving is an indispensable core component of numerous formal verification tools and has found widespread use in industry, in particular when using it in an incremental fashion, e.g. in Bounded Model Checking (BMC). On the other hand, there are applications, in particular in the area of partial design verification, where SAT formulas are not expressive enough and a description via Quantified Boolean...
Numerical integration is a widely used approach for computing an approximate result of a definite integral. Conventional digital implementations of numerical integration using binary radix encoding are costly in terms of hardware and have long computational delay. This work proposes a novel method for performing numerical integration based on the paradigm of logical computation on stochastic bit streams...
High assurance systems require strict guarantees on information flow security and fault tolerance or else face catastrophic consequences. Recently, Gate Level Information Flow Tracking (GLIFT) has been proposed to monitor information flows at the level of Boolean logic. At this level, all flows are explicit which makes it possible to detect security violations, even those that occur due to difficult...
The application of coding strategies is an established methodology to improve the characteristics of on-chip interconnect architectures. Therefore, design methods are required which realize the corresponding encoders and decoders with as small as possible overhead in terms of power and delay. In the past, conventional design methods have been applied for this purpose.
Functional, in contrast to structural, timing analysis is accurate, but computationally expensive in refuting false critical paths. Although satisfiability-based analysis using timed characteristic functions has been proposed, its efficiency and generality remain room for improvement. This paper shows functional timing analysis on industrial designs can be made up to several orders of magnitude faster...
In this paper we explore the impact of data encoding on the design of arithmetic circuits based on residue number system (RNS). Specifically, we show that departing from the conventional representation of residues as integers in weighed binary format and appropriately selecting a non-weighed encoding, efficient circuits in terms of power, area and performance are possible. A quantitative analysis...
Inductive Invariants play critical roles in restricting the search space during Sequential Equivalence Checking (SEC), especially for those instances with few internal equivalent points. For large circuits, there can be too many potential invariants relating signals between the two circuits, thereby requiring much time to prove. However, we observe that a large portion of the potential invariants...
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