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Verification and Validation (V&V) of Systems is an important process in the development of systems, in order to ensure that they are reliable and operational. Among methods of V&V, there are two that seem to be opposite to each other: simulation, which is empirical, and formal verification, which is comprehensive. Moreover, simulation and formal verification propose many different...
Cooperative positioning is a new paradigm in Global Navigation Satellite System (GNSS) positioning. By sharing information with other users and measuring geometrical range between them, the localizability and positioning precision of users can be improved. In this paper, we put forward a two user cooperative positioning model and a positioning algorithm. This paper analyzes the localizability of users...
With the increase in the demand for high performance and high speed VLSI systems such as network processors in networking or SOCs in communication and computing has shifted the focus from traditional performance parameters towards the analysis of power consumption. The power budget and management among the domains of a system is of real concern. Hence, the power aware design using clock gating, power...
A parameterized model for resonant clocking inductors embedded in a dense power grid was developed using extensive electromagnetic simulations. The resulting model was used to support resonant clock designs for the POWER8TM microprocessor. The model enabled tuning of the inductance attached to each clock sector to optimize its resonant behavior, resulting in a 33% reduction in clock power. Simulations...
This paper proposes a procedure based on time-difference of arrival measurements to localize a blind node in an asynchronous network where a set of nodes with known position is present. The proposed method computes the time-difference of arrival of each transmitted signal to any pair of receiving nodes in order to get rid of the unknown transmission time. A range-based localization procedure is implemented:...
This paper presents a Resolver-to-Digital Converter decoding arithmetic for detecting the velocity and driving distance of automobiles. The application deals with dual synchronous reference frame-based phase-locked loop(DSRF-PLL) to transform the sine and cosine output signals of a resolver into the double SRF(DSRF), from which a decoupling cell(DC) added to attenuate oscillations caused by DSRF....
This paper presents an improved ISI shaping technique for multi-bit ΔΣ DACs. Compared to the prior ISI shaping method (Lars Risbo et al, JSSC, 2011) that monitors only the up (0 → 1) transitions, the proposed technique makes use of both the up and down (1 → 0) transitions with negligible hardware cost. It provides a finer control of the transition activity, thereby improving the ISI shaping effect...
We present a fully-digital digital-to-analog converter (FD DAC) architecture design for high-speed communication systems. The FD DAC design is based on the ΔΣ modulation. The specifications for the DAC includes a low 1.2 V supply voltage, a high 5 GS/s input sampling rate, and a wide 2.5 GHz bandwidth. We employ a combination of the time-interleaving, parallel, and pipelining techniques to reduce...
This paper presents a variation tolerant driving technique for all-digital self-timed 3-level signaling high-speed SerDes transceivers. The proposed design generates the 3-level signal without a ½VDD driver, thus removing all the overhead and hassle of an additional supply. Moreover, the proposed all-digital scheme uses half the clock frequency while maintaining the same data rate of the conventional...
Prototyping distributed embedded system can be seen as a collection of many requirements covering many domains. System designers and developers need to describe both functional and non-functional requirements. Building distributed systems is a very tedious task since the application has to be verifiable and analyzable. Architecture Analysis and Design Language (AADL) provides adequate syntax and semantics...
The paging mechanism is widely used in most modern systems to handle the virtual memory. Many page replacement algorithms have been proposed. Therefore, the cor-rectness and reliability of virtual memory management systems become very important. It is essential to formalize and verify the system in a formal way. In this paper, we model the virtual memory management system with MSVL, which is a parallel...
Techniques using modification of power supplies to attack circuits do not require strong expertise or expensive equipment. Supply voltage glitches are then a serious threat to the security of electronic devices. In this paper, mechanisms involved during such attacks are analyzed and described. It is shown that timing properties of logic gates are very sensitive to power glitches and can be used to...
In this paper, a counter based all digital frequency divider is presented. The architecture is based on a counter and a control logic which controls the division ratio. Depending on the control logic circuitry, phase shifting of divided clock signal is also possible. By utilizing both divided signal and shifted signal, fractional ratios are implemented. Phase shifting relies on division factor. Key...
This paper proposes HSTL based energy efficient design of frame buffer for a digital image processor. Our aim is to make energy efficient frame buffer design and for that reason we are using different types of HSTL IO standards. This design is implemented on both Virtex-6 FPGA and Airtex-7 FPGA and compared the power dissipation. It is observed that at 1GHz operating frequency, there is maximum IO...
In this paper, we are implementing green Integrator. Digital integrator is an analog to digital converter. Which is designed in Xilinx ISE14.6 using various IO standard of SSTL in 28nm Kintex-7 FPGA. We are comparing different IO standard of SSTL to get minimum IO power. Via SSTL technology, we achieve green computing with respect to low voltage impedance. We are using different classes of SSTL in...
Phase-Locked Loops (PLLs) are widely used as frequency synthesizers for clock signal generation. In aerospace environment, however, the performance of the PLL can be degraded due to the radiation exposure, which causes degradation of the parameters of its components. Thereby, this article presents a performance analysis of a clock generator PLL under TID effects. Output frequency, power consumption...
In this paper we are presenting result of simulation based energy efficient bi-directional visitor counting machine (VCM) on FPGA (Field Programmable Gate Array). In this work, we have used Xilinx software. We have used different IOs standards that include HSTL_I, HSTL_II, HSTL_I_18, HSTL_II_18, LVCMOS12, LVCMOS15, LVCMOS18, LVCMOS25, and LVCMOS33. For these IOs standard we have collected the total...
In this paper, a throughput-driven design technique is proposed, in which a suspicious timing error prediction circuit is inserted to monitor the signal transitions at some selected check points. Unlike previous works where timing errors are detected after their occurrence, the proposed method tries to use the real intermediate signal transitions for timing error prediction. The check point selection...
The current work proposes a low emission frequency shift keying (FSK) non-PLL based modulator for transmitting neural signals. FSK has been shown to be viable alternative to widely used ASK (Amplitude Shift Keying). Designers need to start developing low Electromagnetic Interference (EMI) algorithms for implanted devices so as to minimize interference. The proposed algorithm utilizes a ramp to modulate...
Testing of VLSI chips are becoming very much complex day by day due to increasing exponential advancement of nano technology. So both front-end and back-end engineers are trying to evolve a system with full testability keeping in mind the possibility of reduced product failures and missed market opportunities. BIST is a design technique that allows a system to test automatically itself with slightly...
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