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The {2^n + 1, 2^n - 1, 2^(2n+1) - 3, 2^(2n) - 2} moduli set and the respective reverse converter have been recently proposed for supporting Residue Number Systems (RNSs). The reverse converter originally proposed was based on the Chinese Remainder Theorems (CRTs), in particular the commonly called new CRTs, and requires at the end a 6nbit carry propagate adder to compute the binary value. In this...
The LSI design methodology against Differential Power Analysis (DPA) is important to realize a tamper-resistant cryptographic circuit. In order to verify the DPA resistance before ASIC fabrication, the DPA verification using FPGA is commonly used. However, power traces of ASIC differ from that of FPGA, so the DPA verification on FPGA cannot guarantee the DPA resistance on ASIC. On the other hand,...
We describe the design and performance of the GRAPE-MPs, a series of SIMD accelerator boards for quadruple/hexuple/octuple-precision arithmetic operations. Basic design of GRAPE-MPs is that it consists of a number of processing elements (PE) and memory components which handle data with quadruple/hexuple/octuple-precision. A GRAPE-MPs processor is implemented on a structured ASIC chip and an FPGA chip...
This article consists of a collection of slides from the author's conference presentation on field programmable gate arrays (FPGA) acceleration. Some of the specific topics discussed include: an overview of the Ivy Bridge architecture and supported applications; power scaling and management facilities; core product features; power efficiency; voltage control and optimization technqiues; power sharing...
Ever-growing era of mobile and personal wireless networks, motivated research in several fields of engineering resulted in low power and low cost consumer products. The voice band processing required in mobile applications demand for architectures, which can easily be integrated in single chip SoC applications. The conventional approach is to have a dedicated IC outside the digital ICs to perform...
This paper addresses the direct optimization of pipelined adder graphs (PAGs) for high speed multiple constant multiplication (MCM). The optimization opportunities are described and a definition of the pipelined multiple constant multiplication (PMCM) problem is given. It is shown that the PMCM problem is a generalization of the MCM problem with limited adder depth (AD). A novel algorithm to solve...
Structured ASICs are designed to bridge the gap between ASICs and FPGAs in terms of cost and performance. By predefining most of the manufacturing masks they highly reduce time-to-market (TTM), non-recoverable engineering (NRE) costs and lithography hazards while exhibiting higher performances than FPGAs thanks to hardwired configuration and interconnections.
Floating point multiplication is a crucial and useful arithmetic operation for many scientific and signal processing applications. High precision requirements of many applications lead to the incorporation of quadruple precision (QP) arithmetics. The logic complexity and performance overhead of quadruple precision arithmetic are quite large. This paper has focused on one of the quadruple precision...
Multiple Context ASIC (mASIC) is a circuit grouping a set of designs (applications) which operates at mutually exclusive times. In this paper we propose to take this particularity into account when we run logic synthesis. The idea is to maximize logic resources sharing between designs to reduce the total resulting area. Once used on mASIC for a set of 5 benchmark designs, our synthesizing technique...
The proliferation of wireless broadband usage over the last decade has led to the development and deployment of multiple broadband wireless radio access technologies (RATs) such as EVDO, WiMAX, HSPA and LTE. To support the ever-increasing wireless traffic demand, researchers have worked on the concept of an integrated heterogeneous wireless environment that encompasses several of these RATs which...
Field Programmable Gate Arrays (FPGAs) provides fast and low cost implementation of DSP systems. The increasing popularity of FPGAs and lack of experience of the DSP algorithm designers on HDLs, makes the High Level Synthesis tools vital for design, early performance estimation, prototyping, testing and verification. In this paper, we present a high-level design-time verifiable Register-Transfer Level...
In this paper, an efficient packing algorithm based on constraint satisfaction problem technique is proposed for contemporary FPGA CLB architecture. No matter how complex the architecture is, there are a limited number of patterns, which can implement all functionalities of FPGA CLB logic. All the patterns are pre-designed and known as reference circuits. The proposed algorithm then matches the reference...
Brazilian government has been investing in microelectronics, especially in hardware education as a strategic factor. In the literature, FPGA-based methodologies have been widely used in hardware and embedded systems design teaching. However, these methodologies don't take into account timing design constraints and an in-depth verification process, essential to understand physical issues, reduce non-recurrent...
The H.264 standard uses integer transform block in its encoder. In this paper, a pipelined architecture of fast 2-D forward integer transform is proposed. For video compression applications such as Television Studio Broadcast or Surveillance Videos, where throughput is of prime importance for real-time encoding, we propose an efficient realization of the forward integer transform unit. Using Xilinx...
This paper addresses the comparison of hardware efficiencies of Intellectual property cores for CAN (Controller Area Network) with LIN (Local Area Interconnect), two prominent protocols for automotive communication. To compare the hardware efficiency of CAN and LIN, methods like area analysis, resource utilization analysis and power analysis on FPGA based prototypes, are used.
Hardware specialization is often the key to efficiency for programmable embedded systems, but comes at the expense of flexibility. This paper combines flexibility and efficiency in the design and synthesis of domain-specific datapaths. We merge all individual paths from the Data Flow Graphs (DFGs) of the target applications, leading to a minimal set of required resources; this set is organized into...
A new single-chip integration approach for industrial applications based on novel mixed-signal and smart-power capable hybrid structured ASIC is presented. The hybrid structured ASIC, offering low non-recurring engineering (NRE) costs of low-voltage (LV) structured ASICs as well as power electronic functionalities of cell based smart-power ICs, provides a cost-efficient integration platform for industrial...
The moduli set has been recently proposed for supporting residue number systems with dynamic ranges of bits. In this brief, we suggest modifying this moduli set to , in order to enlarge the dynamic range to bits. We propose a method that unifies the design of efficient reverse converters for the...
In this paper, we present a Nonlinear Output Error (NOE) model structure implemented on an Application Specific Integrated Circuit (ASIC) chip dedicated to Piecewise Linear (PWL) calculation. Three examples are included to show the performance of the ASIC in quantization, truncation and fixed-point operation. Experimental results and simulation results are shown and compared.
Multiprocessor on chip (MPSoC) with network on chip (NoC) are strongly emerging as prime candidates for complex embedded applications. In a general ESL design methodology and for significant size designs the use of prototyping and emulation through FPGA is necessary for intensive validation and test as well as careful design space exploration. Moving a design from FPGA to ASIC questions the gains...
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