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Confidential Information transactions need cryptographic algorithms to give access to data only for authenticated individuals. In the era of smart phones and internet of things, most of the data exchange occurs between small and smart electronic gadgets. Cryptographic algorithms are necessary in smart gadgets to secure the sensitive data. Hardware implementations of cryptographic protocols on ASIC/FPGA...
Reconfigurable computing (RC) is a compromise of General-propose processor (GPP) computing and Application Specific Integrated Circuit (ASIC) computing with both hardware efficiency and software flexibility. An efficient algorithm to tackle the scheduling and placement problem for the dynamically reconfigurable Field-Programmable Gate Arrays (FPGAs) with real time decisions is highly concerned for...
Background subtraction is an important step for object detection in many video processing systems. This paper presents a low power implementation of mean-filter based background subtraction block in ASIC flow using 65-nm CMOS process technology. The placed and routed ASIC implementation of the background subtraction block achieved an operating maximum frequency of 800MHz. This provides the system...
This paper describes a high performance, low power, and highly flexible cryptographic processor, Cryptoraptor, which is designed to support both today's and tomorrow's symmetric-key cryptography algorithms and standards. To the best of our knowledge, the proposed cryptographic processor supports the widest range of cryptographic algorithms compared to other solutions in the literature and is the only...
Multiply and Accumulate is the main component of the DSP System, which is the major block for power consumption and decides the speed of the overall system due to its complex operation. Hence in most of the DSPs, it lies in the critical path. In this work, Low power MAC architecture has been proposed by examining the critical paths and the hardware complexities. Proposed is a generic architecture...
In this paper we describe a hardware implementation of a low resource digital signature design using Elliptic Curve Digital Signature Algorithm (ECDSA). The implementation of ECDSA is based on the recommended GF (2163) NIST Elliptic Curve Cryptography (ECC). Elliptic curve based systems can be implemented with much smaller parameters, leading to significant performance advantages. Such performance...
Many network security applications such as Intrusion Detection System (IDS), Firewall and Data Loss Prevention System (DLPS) are based on deep packet inspection, in this packets header as well as payload of the packets are checked with predefined attack signature to identify whether it contains malicious traffic or not. To perform this checking different pattern matching methods are used by NIDS....
Hardware fault emulation for Application Specific Integrated Circuits (ASICs) on FPGAs can considerably reduce the time required for the fault simulation. This paper presents a methodology to emulate ASIC faults on state-of-the-art FPGAs. The fault emulation is achieved by following a fully automated process consisting of: constrained technology mapping of ASIC net-list; creation of fault dictionary,...
Mobile Ad hoc network comprises of many nodes which interact with each other through wireless links. It is infrastructure less in nature, due to which attackers can easily attack on the network from any side. There are many attacks which ruin the communication among the nodes of network. Among those attacks there is a Sybil attack that causes severe hazards to the network. Sybil attack is an attack...
For many image processing systems, the computing power required can not be provided by a single sequential processor, this is why many designers appeal to multiprocessor systems (parallelism). This article proposes an original flexible MP-SoC (Multi-Processors System on Chip) architecture for image processing applications. Developing processors network systems tailored to a particular application...
This paper discusses modification to algorithms for computing within a parallel cubing unit. The algorithms discussed in this paper shows several architectures for various operand sizes ranging from 8 to 32 bits. The method proposed in this paper separates the cubing partial product matrix into smaller elements and organizes these partial products into repeatable manageable groups. Consequently, the...
This paper proposed the design and implementation of 1μbar resolution pressure measurement AS IC (Application Specific Integrated Circuit) processing circuit for MEMS capacitive pressure sensor using FPAA (Field Programmable Analog Array) and FPGA (Field Programmable Gate Array). AS IC is designed to measure a pressure for altimeter application in the range of −100 mbar to 900 mbar. It has analog...
In this paper a combined responsive address generator archetypal for WiMAX and WiFi deinterleaver unit aimed for using in wireless broadband system is being proposed. Deinterleaver is used in conjunction with forward error correction unit for eliminating and correcting different transmission errors which occurs when signals are transmitted from base station to subscriber station. Address generator...
This paper proposes the design of AS IC for weather monitoring application and to implement it using FPAA (Field Programmable Analog Array) and FPGA (Field Programmable Gate Array). Three atmospheric parameters such as temperature, humidity and CO2 are considered for experimentation. Sensor signals are ported to FPAA through input ports for analog signal processing. The serial digital output data...
For applications at different X-Ray light sources three pixel array detectors with a common digital readout concept are under development at DESY. All three detectors use an identical digital data acquisition and control board behind sensor and readout-ASIC. A FPGA Framework has been created, which provides generic access to the readout-boards peripherals and which implements fast data transmission...
The PANDA (AntiProton Annihilation at Darmstadt) detector system is under development for the future accelerator facility FAIR in Darmstadt, Germany. In the target spectrometer of PANDA a micro-vertex detector (MVD) will be used as the central tracking detector for charged particles. The design of the MVD is based on silicon strip detectors at the outer layer and on silicon pixel detectors at the...
An implementation of iterative joint detection for multiple access interference using direct-sequence code division multiple access is presented. Results for multiple field programmable gate array (FPGA) and multiple technology nodes for synthesized application specific integrated circuits (ASIC) are presented. The joint detection is based on iterative cancellation known as partition spreading (PS)...
This paper proposes an architecture and Verilog design of fast pipelined Two Dimensional Discrete Cosine Transform (2D DCT) on FPGA with quantization which can be used as a core in video compression hardware. In this design, the methodologies adopted are to use highly parallel and heavily pipelined circuits in order to increase the throughput and to be platform independent, whether an implementation...
Effective implementation of scalar multiplication is vital for Elliptic Curve Crypto-Processor over GF (2m). They have problems in terms of unifiedness and completeness that is overcome by the Edwards Curve. In this paper, the scalar multiplication is done using Non Adjacent Form Algorithm (NAF). We illustrate parallelization in group operation level by utilizing unified addition formulas computation...
The processing capabilities that are included into the acquisition block of the real-time digital oscilloscopes largely contribute to determine the overall performance of the instrument. Their remarkable improvement has made it possible to enhance the performance in terms of increased measurement rate, automation, and reduced measurement uncertainty related to quantization and noise. This paper presents...
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