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Modern embedded systems require all their components, including their microcontroller, to be optimised with respect to the power budget. Two properties are desirable. The first is low power usage and the second is predicable power usage, for improved estimation of firmware performance. In this paper we present all the arithmetic circuits for an ALU of an 8051 microcontroller implemented in Asynchronous...
Design and verification of a novel array multiplier-accumulator architecture, named ABACUS, is introduced in this paper. The design priority in this architecture is low energy operation instead of the traditional `performance-first' approach. ABACUS uses a threshold function to implement multiple fast carry operations in parallel through a cellular array, and therefore significantly deviates from...
In this paper the utilization of Residue Number System (RNS) is investigated as a tool for variation-tolerant design. In particular circuits using various RNS bases are compared in terms of their sensitivity to the variation of process parameters. Furthermore, RNS advantages are quantitatively illustrated by considering a timing model. It is shown that for bases where all moduli channels are candidates...
This paper presents a c-testable motion estimation (CTME) design to efficiently detect the faults in process elements (PEs). The goal of the CTME design is to offer high reliability for video coding systems. The proposed CTME was carried out by Verilog HDL and synthesized with the TSMC 0.18 mum CMOS technology. Logic simulation results show that the proposed CTME guarantees 100% fault coverage with...
Level-testability of multi-operand adders consisting of carry save adders is shown by showing test design for them. A multi-operand adder is a main part of a multiplier. 6L+2 patterns are sufficient to test a multi-operand adder under cell fault model, where L denotes the depth of the multi-operand adder. A test method of the multi-operand adder used as a partial product compressor in a multiplier...
The paper presents a novel high speed and low power 15-4 Compressor for high speed and low power multiplication applications. The proposed compressor uses bit sliced adder architecture to exploit the parallelism in the computation of sum of 15 input bits by five full adders. The newly proposed compressor is also centered around the design of a novel 5-3 compressor that attempts to minimize the stage...
This paper describes the design of a high-performance asynchronous differential equation solver, a common DSP application. The high performance is achieved by two means. First, efficient self-timed datapath elements were designed, including a self-timed carry-bypass adder with low-overhead domino completion-detection and a staggered-evaluation precharged multiplier using carry-save-addition. Second,...
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