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A workfunction-tuned TiN metal gate is integrated into ultra-low-power FDSOI CMOS transistors, optimized for subthreshold operation at 0.3 V. The workfunction of the TiN metal gate is tunable across the mid-gap range, by adjusting deposition parameters and post-deposition annealing. The transistors show 71% reduction in Cgd and 55% reduction in Vt variation, compared to conventional FDSOI transistors...
Since the very beginning of the flash memory era, the market has been dominated by the floating gate technology. However, as floating gate flash continues along a very steep scaling path, more and more barriers start to appear, limiting further scaling possibilities of the technology. At the same time, other concepts are preparing to take over. This paper concentrates on the prospect of high-k materials...
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
ldquoTrenchrdquo capacitors containing multiple metal-insulator-metal (MIM) layer stacks are realized by atomic-layer deposition (ALD), yielding an ultrahigh capacitance density of 440 at a breakdown voltage VDB > 6 V. This capacitance density on silicon is at least 10times higher than the values reported by other research groups. On a silicon substrate containing high-aspect-ratio macropore arrays,...
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