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Reliability is an important design constraint in modern microprocessors, and one of the fundamental reliability challenges is combating the effects of transient faults. This requires extensive analysis, including significant fault modelling allow architects to make informed reliability tradeoffs. Recent data shows that multi-bit transient faults are becoming more common, increasing from 0.5% of static...
Flow-control methods are effective ways to enhance the reliability of Network-on-Chips against transients occurring in deep sub-micron chips. This paper proposes an analytical model to predict the reliability and performance of mesh-based NoCs equipped with flowcontrol methods. In this model, mesh-based NoCs are considered as a network of M/G/1 queues. The iterative solution of the network of queues...
We present hardware performance analyses of Hamming product codes combined with type-II hybrid automatic repeat request (HARQ), for on-chip interconnects. Input flit width and the number of rows in the product code message are investigated for their impact on the number of wires in the link, codec delay, reliability, and energy consumption. Analytical models are presented to estimate codec delay and...
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