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Through Silicon Vias (TSVs) are crucial elements for the reliable operation and the yield of three dimensional integrated circuits (3D ICs). Resistive open defects are a serious concern in TSV structures. In this paper, a post-bond, parallel testing technique is proposed for the detection and location of resistive open defects in TSVs, which is based on easily synthesizable all digital testing circuitry...
The existing communication technologies for IOT have become either saturated or do not meet actual needs, regarding long distances or low power consumption. We propose a study about mobility for the LoRa protocol, a new Low Power Wide Area Network technology. The paper draws upon a short overview of LoRa physical layer protocol, as well as on our testing design, some distances achieved and signal...
Growth of nanometer electronic components increases requirements to testing of the logic circuits. In frame of conventional testing becomes not enough to detect stuck-at faults at circuits' gate poles it is necessary to test timing defects. One of a convenient and popular model of timing defects is path delay faults. A technique of designing a self-checking synchronous network of Finite State Machines...
Tor is an anonymous Internet communication system based on the second generation of onion routing network protocol. Using Tor is really difficult to trace the users Internet activity: this is the reason why the usage of Tor is intended in order to protect the privacy of users, their freedom and the ability to conduct confidential communications without being monitored. Tor is even more used by cyber...
Recurrent neural networks with various types of hidden units have been used to solve a diverse range of problems involving sequence data. Two of the most recent proposals, gated recurrent units (GRU) and minimal gated units (MGU), have shown comparable promising results on example public datasets. In this paper, we introduce three model variants of the minimal gated unit which further simplify that...
As wireless and telecommunicaton infrastructure communications have been integrated into modern vehicle systems (i.e., infotainment systems and vehicle to vehicle systems), the security implications on the relatively unchanged underlying network protocols inside the vehicles are investigated by researchers and industrial experts in the corresponding domain. Some researchers have achieved the investigation...
A surface layer formation by Cs+ bombardment was observed during ultra-thin oxynitride gate dielectrics depth profiling. A significant thickness change relative to ultra-thin layer of oxynitride was noticed when testing a bombarded sample after a period of time. Cs, O and N depth profiles were examined by Dynamic Secondary Ion Mass Spectrometry (DSIMS). The bombarded sample and new sample were investigated...
A simulation study is conducted to model the behavior of the MOS transistor output response with a resistive defect on gate, with both DC and pulse signal inputs. Nanoprobing is performed on actual transistors in DC and pulse modes to validate the simulation. Compared to a reference transistor, a more resistive gate corresponds to a larger rise time in the dynamic pulse response, while the static...
Low frequency noise behavior and hot carrier injection (HCI) effect in 65nm NMOSFET was investigated in this paper. The number of oxide traps and interface traps induced by HCI effect and traps density near silicon oxide interface before and after HCI test were calculated by low frequency noise technology. It was observed that the change during HCI test was determined by low frequency noise technology.
We provide a brief discussion of the basic enhancement mode gallium nitride (GaN) power FET device structure and its performance and then report the results of displacement damage (DD) testing of the Intersil ISL70023SEH and ISL70024SEH GaN power transistors.
We provide a brief discussion of the basic enhancement mode gallium nitride (GaN) power FET device structure and its performance and then report the results of destructive single-event effects (SEE) testing of the Intersil ISL70023SEH and ISL70024SEH GaN power transistors. We include a discussion of a conservative safe operating area (SOA) specification for both devices.
We present the results of single event effects (SEE) testing and analysis investigating the effects of radiation on electronics. This paper is a summary of test results.
This article proposes an approach to generate test cases from BPMN models, for automated testing of Web applications implemented with the support of BPM suites. The work is primarily focused on functional testing and has the following objectives: (i) identify execution paths from the flow analysis in the BPMN model and (ii) generate the initial code of test scripts to be run on a given Web application...
It is the aim of IoT-Testware to supply a rich set of TTCN-3 test suites and test cases for IoT technologies to enable developers in setting up a comprehensive test environment of their own, if needed from the beginning of a project. Initially, IoT-Testware will focus on protocols like CoAP and MQTT. To ensure test and implementation technology independence, the test suites will be realized in TTCN-3...
High-speed cameras are expanding into science laboratories in many disciplines. For example, they can be used for monitoring of the impact testing course, widely spread in evaluation of materials. Usually, they exhibit a slight delay between the trigger pulse was applied and the recording was started. For many applications, this delay may be critical. The authors of this paper have faced two problems:...
Testing digital circuits is crucial for guaranteeing the correct and reliable functioning of electronic devices. Deriving high quality test suites to check the correctness of such devices is an important task. To estimate the quality of a test suite, a common approach is to simulate faults in a given circuit specification and to assess the fault coverage of the test suite. In this paper, we propose...
Error-tolerance is a notion that focuses on evaluating the acceptability of errors by considering the insensitivity of human beings to minor vibrations in multimedia applications. In this paper we will show that this notion can relax the functional test requirements of a target circuit. Rather than finely grading the quality of the output results as conventional methods do, we only need to decide...
The problem of determining the sensitization probability of a path by a test vector is investigated. It is important when testing for delay defects due to process variations. An algorithm is presented which has high accuracy. Gate delays are modeled as probability mass functions, and novel operations are introduced that take into consideration circuit reconvergences and path correlations. Experimental...
An automatic, defect-oriented method is proposed for activating latent defects in analog and mixed-signal integrated circuits. Based on the topology modification technique, added stress transistors generate voltage stress that activates these latent defects. This contrasts with burn-in testing which uses increased temperatures as a fault activation mechanism. Moreover, this Design-for-Testability...
Mismatch of power supply integrity between an ATE and a customer board in semiconductor test can lead to test failures such as overkills and underkills. A technique is required to control the power supply impedance of an ATE by feedback control using compensation current injection so that it emulates the impedance of a customer board, eliminating test failures coming from the impedance difference...
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