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The quality level of mixed-signal ICs lags behind the below-part-per-million defect test escape rates of digital ICs, as a result of the traditional testing based on performance specifications. Methods increasing the controllability to solve the problem of the low fault coverage of analog and mixed-signal circuits are in practice limited due to the excessive area overhead they require and their impact...
Ramsey theory assures us that in any graph there is a clique or independent set of a certain size, roughly logarithmic in the graph size. But how difficult is it to find the clique or independent set? If the graph is given explicitly, then it is possible to do so while examining a linear number of edges. If the graph is given by a black-box, where to figure out whether a certain edge exists the box...
This paper aims toward joining the ideas of OBT (oscillation-based testing) and DFT (design for testability). It gives insight into an optimization process that provides testability if one chooses to use the OBT. The optimization procedure is exemplified on a timer device NE555. Utilization of a timer circuit allows avoidance of a specific design of the feed-back loop. The optimization procedure is...
This paper introduces a kind of simulation testing system scheme for train-borne controller and applies it to the simulation testing system of the controller. Besides, it elaborates the system structure, interface type and key module of the hardware realization. The simulation testing system for train-borne controller is completely built, and plays a vital role in the train-borne controller simulation...
Through Silicon Vias (TSVs) are crucial elements for the reliable operation and the yield of three dimensional integrated circuits (3D ICs). Resistive open defects are a serious concern in TSV structures. In this paper, a post-bond, parallel testing technique is proposed for the detection and location of resistive open defects in TSVs, which is based on easily synthesizable all digital testing circuitry...
In this study, the condition of high-voltage three-phase SF6 circuit breakers is assessed using analysis of variance-based statistical test. 40 SF6 circuit breakers, with similar technical characteristics and operating conditions, were tested on the field using the SA10 switch analyser. The chi-square test for normality was performed on the measured coil tripping times, before analysis of variance...
This paper is devoted to a problem of on-line testing efficiency in digital components of safety-related systems taking into account their design for operation in two modes: normal and emergency. Approach to increase of on-line testing method trustworthiness in checking of approximate results is offered. Approach is based on distinguishing of the essential and inessential errors caused by faults of...
This paper presents a technique for the fault-based test of the analog amplifiers. The circuit defects are modeled with the 2-fault transistor models. The test method combines the amplifier evaluation both in and out of the normal operating region, with the transconductance of the amplifier being the key test parameter. Furthermore, the additional low current test is employed in order to maximize...
Management systems based on elementary relay background are ubiquitous within railways of endless Post Soviet Union expanse. The aforesaid systems considered as rather robust ones with provision of high level safety, which may solve the task reckoning contemporary rail stock transportation supervision. Hence, with actual speed enhance routine, being conducted on railway tracks, structural defects...
This paper presents hybrid L- and P-stable implicit numerical methods for solving differential equations of electronic circuits and systems. Hybrid methods are developed on the basis of two known subclasses of implicit Runge-Kutta methods commonly referred to as Rado IIA and Lobatto IIIA methods. Comparative analysis of the known methods and the proposed hybrid methods demonstrates a high accuracy...
This paper reports characterization and analysis of diode string electrostatic discharging (ESD) protection structures fabricated in a foundry 28nm CMOS technology. Comprehensive measurements were conducted using very-fast transmission line pulse (VFTLP) tester for Charged Device Model (CDM) ESD protection. The analysis results reveal the I-V insights critical to practical ESD protection designs.
The paper includes results of the theoretical research and practical application of soft-processors testing, in particular Nios compiler of Altera SoPC Builder core. The model is based on Model-Based Testing concept. ForSyDe programming formal language is used as instrument for the development of soft-processor reference program model. Stages of model development with the follow-up analysis and comparison...
Digital microfluidic biochip (DMFB) is an attractive platform for immunoassays, point-of-care clinical diagnostics, DNA sequencing, and other laboratory procedures in laboratory experiments due to its flexible application and low fabrication cost and further for the development of instruments. As being applied for these safe-critical applications, on-line testing methods are required to ensure robust...
The paper is a continuation in a series that identifies more of the developing issues in relay testing - what was once well understood in a protection element's response is today a challenge in testing modern protection systems. Modern algorithms and the complexity of the combined protection element(s) scheme logic creates variable and sometimes unacceptable testing results when compared to manufacturer...
This paper presents a new scan-based at-speed test signal scheme called One Clock Alternated Shift (OCAS) for minimizing the potential impact of the power distribution network PDN impedance variation. The strategy behind this new scheme is to mimic the clock signal of the functional mode as closely as possible. As a case study, we consider the PDN impedance variation that can occur with 3-D ICs, more...
Despite analog SPICE-like simulators have reached their maturity, most of them were not originally conceived for simulating faulty circuits. With the advent of smart systems, fault testing has to deal with models encompassing both analog and digital blocks. Due to their complexity, the industry is still lacking of effective testing approaches for these analog and mixed-signal (AMS) models. The current...
In the last years, the phenomenon of electronic products passing all tests by the manufacturer but failing in the field (No Fault Found, or NFF) attracted the attention of industries and researchers. Delay faults are supposed to be among the contributors to this phenomenon. Hence, companies are increasingly adopting functional test as a final step, which is expected to detect this kind of defects...
A variety of fault models have been defined to capture the behaviors of commonly occurring defects and ensure a high quality of testing. When several fault models are used for test generation, it is advantageous if the existence of an undetectable fault in one model does not imply that a fault in the same component but from a different model is also undetectable. This allows a test set to cover the...
The increasing demand for clean energy and sustainable living have been promising for Photovoltaic (PV) systems. However, in urban environments, uniform solar insolation is not guaranteed. Thus, conventional Maximum Power Point Tracking (MPPT) techniques severely fail at Partially Shaded Conditions (PSC). In response, a new hybrid technique is being proposed using Adaptive Network-Fuzzy Inference...
Oscillation based testing (OBT) has proven to be a simple yet effective VLSI test for numerous circuit types. In this work, OBT is applied to test Second-generation Current Conveyor (CCII) based filters for the first time. Adopting a CCII-based band pass filter as a case study, it is shown that OBT can be implemented with a minimally intrusive switched feedback loop to establish the oscillator. Exhaustive...
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