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Dual-core platforms are growing as a new industry trend as platforms with only one core cannot easily perform the diverse functions in current embedded system applications, such as smart phones. We establish an easy-to-use co-simulation dual-core virtual platform to validate the functionality of hardware and software jointly. In our platform, the hardware components are implemented by SystemC, and...
In this paper, an efficient VLSI architecture for convolutional code decoding algorithm is presented. This algorithm locates all erroneous segments of the received sequence and then applies our proposed decoder to these segments only. Besides, the clock-gating technique is used to disable the non-working registers of our design to further reduce the power consumption efficiently with no bit error...
The re-encoding and coordinate transformation techniques are usually employed to reduce the computational complexity of interpolation, which is the most computation-intensive step in the algebraic soft-decision decoding of Reed-Solomon (RS) codes. In this paper, we present a high-throughput re-encoder design for soft-decision decoding a (255, 239) RS code. With the developed scheduling scheme and...
This paper presents the power-performance trade off of three different cache compression algorithms. Cache compression improves performance, since the compressed data increases the effective cache capacity by reducing the cache misses. The unused memory cells can be put into sleep mode to save static power. The increased performance and saved power due to cache compression must be more than the delay...
In this paper, we give an introduction to Chinese standard Universal Transport Interface (UTI) for digital television receiving devices. UTI standard, with independent intellectual property rights, is based on the high speed USB2.0 physical interface. It has two logical interfaces: TS interface and command interface. It aims not only to support the conditional access (CA) service, but also to support...
This paper presents the architecture and the corresponding simulation results for a digitally interfaced ultra-low power extended Hamming decoder implemented in analog integrated circuitry. ST's 65nm low power CMOS design library was used to simulate the complete decoder including a serial input digital interface, an analog decoding core and a serial output digital interface. The simulated bit error...
A new kind of logging device was designed based on Nios II technology. The device make use of Nios II processor which was embedded in FPGA to achieve depth processing, tension, magnetic marks acquisition, Manchester code through custom components. The logging system based on Nios II technology has some features such as simple hardware structure, stable and reliable performance; it could be realized...
A design method of 5B6B codec of digital optical terminal adopted very-high-speed integrated circuit hardware description language (VHDL) based on Altera development system and Quartus2 of software development is presented through the research on optical fiber transmission code mBnB in this paper, the system has strong portability, flexibility and high running speed. Finally, the feasibility and advance...
This paper investigates the feedback stabilization problem for networked control systems (NCSs) with unknown disturbances, where sensors and actuators communicate with a remote controller over a multi-purpose network. A new control scheme, which relies on both information-theoretic and control-theoretic tools, is proposed to stabilize linear discrete-time plants. A sufficient condition for stabilization...
In this paper we introduce the implementation of a block-LDPC codec on FPGA with simulation. The result shows that this codec is suitable for block LDPC with less resource consumption.
This paper investigates the stabilization problem for networked control systems (NCSs) with limited data rates over an additive white Gaussian noise (AWGN) channel. The notion of control with limited data rates means specifying the lower bound of data rates, above which there exists a coding and control scheme for stabilization of linear time-invariant systems. Different from the literatures, the...
Because of the high computation demand for multimedia applications like video decoding, there is a need to develop flexible and high performance reconfigurable computing architectures. Taking video decoding algorithm as an example, we propose a reconfigurable computing realization solution of multimedia application. Based on the analysis of parallelism in video decoding algorithm, a hardware platform...
Bitrate adaptation and higher compression ratio are the major issues in world of Video compression. H.264 is the latest standard for video compression with high flexibility in compression ratio, quality of video and rate adaptation. This paper explores the possibility of bitrate reduction and proposes an algorithm to calculate the cost of each 8x8 subMacroblocks. Based on the threshold and the cost...
This paper provides on effective Shuffled Embedded Technique (SET) to eliminate the drawback of substitution technique. Using the genetic algorithm, message bits are embedded into multiple, vague (blurred) and higher LSB layer in order to increase robustness, which is achieved by embedding secret messages in digital audio stream. Additional careful considerations are taken against the premeditated...
This paper maps channel codes at the application layer to data-partitioned video so that more important compressed data are protected in a closed-loop communication scheme. In particular, window-growth rateless codes are a priority-scalable form of Forward Error Correction that also provide incremental protection to streamed video. The paper introduces a detailed scheme for achieving this according...
Fountain codes provide an efficient way to transfer information over erasure channels like Internet. LT codes are the first codes fully realizing the digital fountain concept. The key to make LT codes work well is the degree distribution used in the encoding procedure, which is sampled to determine the degree of each encoding symbol. This paper propose a revised robust soliton distribution which has...
We present a Fourier-analytic approach to list-decoding Reed-Muller codes over arbitrary finite fields. We use this to show that quadratic forms over any field are locally list-decodeable up to their minimum distance. The analogous statement for linear polynomials was proved in the celebrated works of Goldreich-Levin and Goldreich-Rubinfeld-Sudan. Previously, tight bounds for quadratic polynomials...
A locally decodable code encodes a message by a codeword, such that even if the codeword is corrupted by noise, each message bit can be recovered with high probability by a randomized decoding procedure that reads only few bits of the codeword. Recently a new class of locally decodable codes, based on families of vectors with restricted dot products has been discovered. We refer to those codes as...
Low density parity check code (LDPC) has constructed a flexible, low decoding complexity and performance close to Shannon limit benefits. This paper introduces the LDPC codes and bit-interleaved coded modulation with iterative decoding (BICM-ID) scheme, given its log-likelihood ratio belief propagation (LLR-BP) decoding algorithm. Achieved with LDPC codes as component codes in BICM-ID scheme is applied...
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