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Polar codes are a family of error correcting codes that achieves the symmetric capacity of memoryless channels when the code length N tends to infinity. However, moderate code lengths are required in most of wireless digital applications to limit the decoding latency. In some other applications, such as optical communications or quantum key distribution, the latency introduced by very long codes is...
LDPC codes are a family of error correcting codes used in most modern digital communication standards even in future 3GPP 5G standard. Thanks to their high processing power and their parallelization capabilities, prevailing multi-core and many-core devices facilitate real-time implementations of digital communication systems, which were previously implemented on dedicated hardware targets. Through...
In this paper, compact memory strategies for partially parallel Quasi-cyclic LDPC (QC-LDPC) decoder architecture are proposed. By compacting several adjacent rows hard decisions and extrinsic messages into one memory entry, which not only reduces the number of memory banks for hard decisions, but also facilitates multiple data accesses per clock cycle, the throughput of the decoder is increased. We...
In this paper, we propose a feedback-aided irregular repetition slotted ALOHA (F-IRSA) protocol which depends on the distance between the received packet and the set of packets already recovered at the receiver. We employ feedback messages to terminate the user retransmission process, and use successive interference cancellation (SIC) for packet recovery. We evaluate the number of transmissions per...
Dual Connectivity(DC) is one of the key technologies standardized in Release 12 of the 3GPP specifications for the Long Term Evolution (LTE) network. It attempts to increase the per-user throughput by allowing the user equipment (UE) to maintain connections with the MeNB (master eNB) and SeNB (secondary eNB) simultaneously, which are inter-connected via non-ideal backhaul. In this paper, we focus...
This paper presents a new high-throughput, low-complexity Bit Flipping (BF) decoder for Low-Density Parity-Check (LDPC) codes on the Binary Symmetric Channel (BSC), called Probabilistic Parallel Bit Flipping (PPBF). The advantage of PPBF comes from the fact that, no global operation is required during the decoding process and from that, all of the computations could be parallelized and localized at...
The continuing trend towards higher data rates in wireless communication systems will, in addition to a higher spectral efficiency and lowest signal processing latencies, lead to throughput requirements for the digital baseband signal processing beyond 100 Gbit/s, which is at least one order of magnitude higher than the tens of Gbit/s targeted in the 5G standardization. At the same time, advances...
Model of Turbo-Product Codes decoder architecture and method for construction of Turbo-Product Codes decoder are proposed in the paper. The model describes decoder functioning taking into account limitations of hardware platform and proposes re-use of components in the decoding process. The method provides set of steps for decoder implementation. Field-Programmable Gate Arrays circuits are selected...
Increasing data traffic and multimedia services in recent years have paved the way for the development of optical transmission methods to be used in high bandwidth communications systems. In order to meet the very high throughput requirements, dedicated application specific integrated circuit and field programmable gate array solutions for low-density parity-check decoding are proposed in recent years...
This paper proposes Raptor codes-structured wireless super-dense networks serving a massive number of users with passive nodes constructing a precode of Raptor codes for future wireless networks. Passive nodes do not have their own information and only forward information from the neighboring nodes to the destination node. Similar to the capability of precode of Raptor coding scheme to protect information...
The degree to which Turbo-Code decoder architectures can be parallelized is constrained by requirements for flexibility with respect to code block sizes and code rates. At the same time throughput requirements are expected to increase by a factor of up to 20x for 5G networks, which are currently undergoing standardization. The limiting factors for the throughput of a Turbo-Code decoder are maximum...
Although, it was shown that NC is a promising technique to improve the throughput; especially for multicast environment; it also bears negative side-effects (e.g., high decoding delay). Since streaming video are usually subject to strict delay constraints, high decoding delay must be resolved to enhance the performance of the NC schemes. To overcome this issue, this paper presents a new scheme named...
Viterbi detectors are widely used in data recording channels in the timing loop as well as in the digital back end before error-correction decoding to detect data in the presence of inter-symbol interference (ISI) and noise. Further, soft reliability values assist in the decoding of outer codes. The state-of-the-art implementations of the Viterbi algorithm are synchronous which consider the ‘worst-case’...
A Decoder working on the logic of LDPC is designed for a 8 bit Logical ALU. The Simulation has been done to minimize the Voltage Leakage and Maximum throughput.
In order to improve the throughput of error correction decoding for the high-performance solid-state drives (SSDs), a semi-parallel low-density parity-check (LDPC) decoding architecture is proposed in this paper. The circuit of the LDPC decoder which can be dynamically configured with bit rate and code length is implemented using the scheduling control flow mode of single instruction multiple data...
Belief propagation (BP) polar code decoder is well-studied from many aspects. This study proposes a hardware optimization to improve performance of polar BP decoder by modifying both processing element (PE) and early stopping criterion (ESC). PE is optimized by using high-speed parallel-prefix Ling adder instead of carry ripple adder and WIB ESC introduced in literature is optimized by removing unnecessary...
Convolutional encoder is widely applied in lots of wireless communication standards including 3G/4G mobile communications, DVB (Digital Video Broadcasting), IoT(Internet of Things) transmissions and so on. Therefore multi-standard Viterbi decoder design for the above receivers is a hot issue. In this paper, a reconfigurable high performance Viterbi decoder design is proposed for LTE, WiMAX, CDMA2000,...
Panoramic streaming enables users to interactively navigate through high-spatial resolution videos and create an immersive and personalized user experience. Since transmission of high-resolution videos in desirable quality is not feasible given the limited throughput of access and home network links, our work is based on tile-based streaming, where only a spatial subset of the video is transmitted...
This paper presents a fully pipelined layered decoder architecture for IEEE 802.11 n/ac/ax LDPC codes, free of idle cycles. Several decoder architectures for such codes have emerged in the literature featuring throughputs in the multi- Gbps range. The proposed architecture surpasses the highest reported throughput for IEEE 802.11 n/ac/ax LDPC codes. This is achieved 1) algorithmically, by implementing...
This paper proposes a layered decoder architecture for array QC-LDPC codes which targets tens of Gbps data rates. It relies on layer unrolling with pipeline stages in between layers, allowing simultaneous decoding of multiple layers. The most important features of the proposed decoder are: (i) fully parallel processing units within each layer (ii) hardwired layer interconnect that allows the removal...
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