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Through Silicon Vias (TSVs) are crucial elements for the reliable operation and the yield of three dimensional integrated circuits (3D ICs). Resistive open defects are a serious concern in TSV structures. In this paper, a post-bond, parallel testing technique is proposed for the detection and location of resistive open defects in TSVs, which is based on easily synthesizable all digital testing circuitry...
Comparators are a critical element of Analog-to-Digital converters (ADCs) intended to operate in a harsh environments such as the automotive. The influence of temperature on key comparator properties such as the delay must be well understood to maximize their speed. In this paper a Double-Tail latch analysis leads to an analytical expression for the delay to more accurately guide the design over a...
A model of copper and carbon nanotube (CNT) composite filled through silicon via (TSV) is developed to estimate signal delay of a novel interconnect, employed in 3D integrated circuit (IC) design. The main objective of 3D interconnect is to electrically connect two stacks of circuits and offer robust chip functionalities. The 3D integration scheme allows independent design of operational blocks in...
Due to the scaling of devices in nanometer regime speed and power related issues rises in digital circuits. Carbon nanotube field effect transistor (CNTFET) has been used in the present work as a low power circuit element. The major advantage of CNTFET is low power and energy consumption as compared to the conventional CMOS. This paper proposes the basic implementation of CNTFET inverter, MUX and...
Arithmetic and Logic Unit represent the core of all microprocessors. It performs arithmetic and logical operations. ALU is getting more complex and smaller to make more efficient circuits. This paper describes simple ALU but contains the essentials functions. It is a reconfigurable ALU based on double gate carbon nanotube field effect transistors (DG-CNTFETs). The proposed ALU is designed for one...
This article considers the problem of constructing an adaptive control system for nonlinear priori uncertain dynamic object with statement delay and relative order greater than one. As methods of solving the hyperstability criterion and high-speed self-tuning correction unit are used.
In the research the load balancing routing model in Time-Sensitive Networks is proposed. The novelty of the solution is a type of optimality criterion, the use of which minimizes the circuit delays. The proposed solution is compromise in terms of computational implementation as compared to the previously known models, in which the equality of the circuit delays of packets were considered as limitations,...
The carbon nanotube field-effect transistor (CNFET) is a potential candidate to replace MOSFET due to advantages offered by CNFET such as its superior electrical, thermal, and mechanical properties. When designing circuits made of CNFETs, additional features such as the CNT number, positions and pitch in the array of tubes creating a transistor channel must be considered for performance evaluation...
The current study is dedicated to the investigation of stability issues occurring in switching power converters with non-ideal feedback circuitry. The interaction of nonlinear effects caused by the introduction of delay in the control circuitry of the compensated boost converters is studied by means of complete bifurcation diagrams, exploiting discrete-time modeling approach. The effectiveness of...
Multiplier is one of the major hardware circuits of microprocessor and high performance systems such as digital signal processor; FIR filters, processing operations like Convolution, Cross Correlation, and auto-correlation of discrete signals, digital Image processing applications such as edge detection etc. The major design constraint of multiplier is speed which is affected due to propagation delay...
The Delay and Speed plays a complementary role in ICs, as the delay decreases the speed increases and vice-versa. The scaling of MOSFETs has resulted in reduction in size of ICs. As we scale down to nanometer regime, the Short Channel Effects (SCEs) of MOSFET affects the system performance and reliability. Here in this paper we discuss on FinFET, which is an alternate MOSFET, through which the SCEs...
With continuous scaling of VLSI technology, coupling capacitance between interconnects lines need more accurate transmission line modelling, requiring the introduction of self and mutual inductances. Self and mutual inductances can cause for crosstalk noise and delay between high speeds VLSI interconnects. This paper presents an mathematical computation of crosstalk noise of ‘L’ Type RLC global interconnects...
Electromigration (EM) in signal interconnects can induce voids, and the evolution of these voids may cause the wire resistance to increase with time. Previous approaches use the mean time to failure metric based either on a fixed resistance increase or open circuit failure criterion. This work shows that even noncatastrophic EM on critical paths may cause performance degradation, resulting in incorrect...
This paper proposes an effective model for evaluating vertical signal propagation delay in through silicon via (TSV) based three-dimensional integrated circuits (3-D ICs). The capacitance model for on-chip interconnects is also proposed. All parasitic parameter values for an entire structure can be calculated by the closed-form equations. The delay model is constructed with the first- or second-order...
Carbon Nano-Tube Field Effect Transistors (CNFETs) are considered to be a promising candidate beyond the conventional CMOSFET. It is due to their higher current drive capability, ballistic transport, lesser power delay product and better thermal stability. CNFETs specific parameters, such as number of tubes, pitch (spacing between the tubes) and the diameter of CNTs determine current driving capability,...
This paper present an analytical model of delay for subthreshold voltage to time converters (VTCs). The model characterizes an equation between the input voltage and output delay. Delay prediction model can be used to compute delay and understand characteristic of VTC in subthreshold region. Simulations are done in 0.18um CMOS technology and results ensure the accuracy of the model.
The focus of the present research is to design a receiver circuit for high speed and high throughput data transmission over the interconnect line. This is achieved using current mode signaling in interconnects. In the present paper an efficient receiver for current mode interconnect system is proposed. The analysis shows that the proposed receiver has 26.65% lesser latency at room temperature for...
Multiple Dynamic Supply Voltage (MDSV) is a technique that focuses on reducing the dynamic power. This technique is an evolution of the Multiple Supply Voltage (MSV). MSV and MDSV introduce some difference on traditional physical synthesis due to the different voltage operations of each region in the design. To convert the voltage among regions supplied by different voltages, these techniques insert...
In the proposed work, crosstalk effects are investigated in two identically coupled SWCNT bundle interconnects at 21 nm and 15 nm technology nodes for intermediate and global interconnects. An ABCD parameter based approach has been used to investigate crosstalk delay and noise in both sparse and dense SWCNT bundle interconnect system. The simulation results show that the proposed model is not only...
In this work the IBIS is employed to estimate the adverse effects of package wheresome modifications in its representation are proposed. IBIS is a standard file type which is widely popular in system design level. Many vendors, designers, and circuit simulators produce, use, and accept this standard nowadays. It represents the behavior of the I/O buffer of digital circuit considering their package...
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