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For 7 series Xilinx FPGAs, this paper shows that it is risky to believe that so fundamental operation as data delay must be always implemented without wasting chip area, even when design tools are not especially guided by a developer. Against this background, two solutions are presented that allow for minimizing the area occupied by flip-flops used to delay data that comes from outside the slices...
To mitigate the total power consumption in any circuit, ASICs or FPGAs, various conventional power gating techniques has been adopted depending upon the need of the application, dynamically controlled power gating procedure is one such power gating technique which can be used to reduce the total leakage power consumption of the circuit during the runtime. It can be applied on the real time application...
In this document we implemented several digital and filtering techniques in real time using Xilinx Zynq-7010 FPGA To achieve this we use a high level programming language like NI LabView to generate the VHDL that will be recorded in the hardware. We expose the mathematic characteristics of each one of the effects and the impact in the processing of the audio signal. We also compare with those we obtained...
Nowadays some High Level Synthesis (HLS) tools are introduced which are able to generate Hardware Description Language (HDL) codes from high level floating point arithmetic expressions for implementation on FPGAs. Before this conversion, changing the form of high level expressions usually leads to significant improvements in the final implementation in terms of accuracy, resource usage and latency...
In this paper, we present a performance comparison of Binary Coded Decimal (BCD) Adders on Field Programmable Gate Logic (FPGA) for functional and behavioural verification. Although it does not prove that the circuit is reversible, implementation on FPGA serves as a platform for functional verification of circuits. BCD adders are one such circuit which has gain wide research emphasis where BCD adders...
An adjustable pulse module with FPGA-based 0.1 ns resolution is designed, which has the function of simultaneously generating multi-channel pulse. Various pulses time delay can be adjusted each other. Therefore it can improve the small target RCS (radar cross section) test accuracy under the complex environment. At present, the technology is successfully applied to a RCS tester.
A low power CMOS Static Random Access Memory (SRAM) based Field Programmable Gate Arrays (FPGA) architecture is being presented in this paper. The architecture presented here is based on CMOS logic and CMOS SRAMs that are used for on-chip dynamic reconfiguration. This architecture employs the fast and low-power SRAM blocks that are based on 10T SRAM cells. These blocks are employed in fast access...
The testing, verification and evaluation of wireless systems is an important but challenging endeavor. The most realistic method to test a wireless system is a field deployment. Unfortunately, this is not only expensive but also time consuming. In this paper, we present the design and implementation of a digital wireless channel emulator, which connects directly to a number of radios, and mimics the...
With rising demands for high-performance computing and design flexibility of post-fabrication system, reconfigurable architecture has been drawing increasing attentions. However, reconfigurability, advantage of current Field-Programmable Gate Array (FPGA), is severely limited by small capacity of on-chip Static Random Access Memory (SRAM) for storing configuration bits. With emerging high-density...
Incorporating Networks-on-Chip (NoC) within FPGAs has the potential not only to improve the efficiency of the interconnect, but also to increase designer productivity and reduce compile time by raising the abstraction level of communication. By comparing NoC components on FPGAs and ASICs we quantify the efficiency gap between the two platforms and use the results to understand the design tradeoffs...
Transistor aging mostly due to Negative and Positive Bias Temperature Instability (NBTI and PBTI) is a major reliability threat for VLSI circuits fabricated in nanometer technology nodes. As much as FPGAs benefit from the most scaled and advanced technologies, they become more susceptible to transistor aging. In this paper, we investigate the effect of transistor aging on programmable routing resources...
Cluster-based logic blocks from most commercial FPGA products do not have an input bandwidth constraint, i.e., limiting the number of signals going from routing channels into the block. We show that high quality packing for such logic blocks can be easily achieved based on k-way partitioning. We implemented 2 such packing tools: PPack (routability-only) and its timing driven version TPPack. Experimental...
Due to their different cost structures, the architecture of switches for an FPGA packet-switched Network-on-a-Chip (NoC) should differ from their ASIC counterparts. The CONNECT network recently demonstrated several ways in which packet-switched FPGA NoCs should differ from ASIC NoCs. However, they also concluded that pipelining was not appropriate for the FPGA switches.We show that the Split-Merge...
In general applications such as image processing signal processing and many similar applications find most of the work is done through multipliers to execute complex instructions. We generally use low order compressors for this multiplication operations. In this proposed paper, we are using higher order compressors to execute the multiplication operation. As these compressors have less delay, low...
Retiming is a transformation which can be applied to Digital Signal Processing Blocks that can increase the clock frequency. Folding in retiming can also reduce the resource utilization and power consumption. This transformation requires computation of critical path and shortest path at various stages. In this particular work, a FPGA based path finder is designed to compute critical path and shortest...
A Wallace tree multiplier using Booth Recoder is proposed in this paper. It is an improved version of tree based Wallace tree multiplier architecture. This paper aims at additional reduction of latency and area of the Wallace tree multiplier. This is accomplished by the use of Booth algorithm and compressor adders. The coding is done in Verilog HDL and synthesized for Xilinx Virtex 6 FPGA device....
This paper presents aspects of process technology applicable to FPGAs. Overdrive of transistors for routing pass gates is an important performance and reliability factor. Random variation effects are significant for small arrays of configuration RAM, but small impact on performance. We discuss challenges for CRAM and switch replacement using novel technologies.
A multi-GHz arbitrary timing generator (ATG) design is described and demonstrated in a hardware prototype. The objective of the ATG is to realize ATE hardware that nearly matches the unlimited timing flexibility of software simulation tools. The ATG allows timing edges to be programmed at almost any desired point within the test, with minimal constraints. The delay of every edge can be changed on...
Analysis of digital design and implementation of Nam Quoc Ngo's 32 bit integrator is being presented in this paper. The design objective is to realize a wider bandwidth integrator. Proposed design is optimized using conditional sum adder for addition, Radix 4 Booth with Wallace tree carry save adder algorithm for multiplication and a modified algorithm to calculate 2s complement of a binary number...
In this paper, in order to reduce discretization errors of dynamics with variable structures (VS), we propose an improved digital integrator. Use of Richardson extrapolation (RE) and fractional delay (FD) can improve Euler integrator, so we can obtain an improved integrator. However, Euler integrator using RE and FD directly has an infinite gain at a Nyquist frequency, and it is unsuitable for integrations...
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