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The capability to ensure reliability while operating in extreme environments is important for the most demanding automotive applications. Even though pressure sensors are a well-established area in the MEMS industry, improvements in sensor design are needed to deliver reliability and long operational life. This paper reports the design, fabrication and testing of a harsh media backside absolute piezoresistive...
Metal-insulator-semiconductor capacitors used as a RC snubber attenuate voltage overshoots which may occur during switching phases. These devices feature good temperature stability up to 200°C and can be integrated very close to power switches on the same transfer substrate. As the capacitors need to withstand high voltages in most applications, thick dielectric layers have to be used, causing significant...
Charge trapping properties of Al-ZrO2/Al2O3/ZrO2-SiO2-Si structures were investigated in attempt to elucidate the instability in their C-V hysteresis. The hysteresis in these structures is mainly due to subsequent trapping of electrons and holes injected from the Si substrate. However the competitive process of electron injection from the gate accompanied by the high leakage introduces instability...
This paper presents a compensation method for the stress dependence of flexible integrated capacitive pressure sensors. Without compensation the differentiation between changes in the sensor signal due to pressure or bending cannot be made [1]. To achieve this requirement a complex back side structuring of thinned capacitive pressure sensors is conducted in preparation for simulations and pressure...
This paper presents a new CMOS stress sensor readout method based on the ratiometric measurement principle. A unique feature of this method is to simultaneously detect the in-plane stress magnitude and angle. The sensor core is a cascoded current mirror structure consisting of a reference input branch and four output branches with MOSFETs in 0°, 45°, 90° and 135° layout orientations. Current ratios...
The lifetime of power DMOS devices subjected to Thermal Induced Plastic Metal Deformation (TPMD) is highly dependent on the design of the metallization systems and thus requires the understanding of temperature, stress and strain distribution. This paper introduces and studies via numerical simulations with finite element method (FEM) a simple three dimensional (3D) transistor substructure commonly...
Amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) Thin-Film Transistors (TFTs) integrated with Si based CMOS processes is an emerging technology in ultra-low power applications. ESD characteristics of a-IGZO TFTs with a Si substrate are studied and compared to their characteristics on traditional foil/glass substrate. The ESD performance is shown to be improved, thanks to improved thermal properties of...
The Integrated Fan Out (InFO) technology can accom-plish package miniaturization and successfully achieve “More than Moore's Law.” Its substrate-free technology also brings great cost-effective attraction to mobile and wearable applications. Ultra-thin integrated passive devices (IPDs) with high capacitance density can further shrink the InFO size and boost the bandwidth. Although the cost for the...
Ge is expected as a channel material for the next generation MOSFET because the electron mobility is larger than that of Si. The a-Ge films were deposited on a quartz substrate by an electron beam evaporation at RT. The thicknesses of Ge films were 15, 30, and 60 nm. The SiOx capping films (10 nm thickness) were deposited on the a-Ge films by a reactive sputtering as a capping film. The crystallization...
Degradation behavior of thin-film Si photovoltaic modules by hygrothermal and thermal cyclic stresses was studied. Degradation progresses along the scribe lines for integration and from the slit on back sheet for taking out interconnector ribbons. Not only acetic acid generated by hydrolysis reaction between ethylene-vinyl acetate encapsulant and penetrating water vapor but also water vapor itself...
A finite element model which contains one sixth of the IGBT module based on a real test chip of IGBT module is established to investigate the temperature and stress distribution of different shape bonding wire. The finite element (FE) analysis which coupled electro-thermal and thermal-mechanical are conducted using commercial software ABAQUS. The thermal performance and stress distribution of IGBT...
A simulation analysis of a porous nanocrystalline silicon membrane (pnc-Si) is conducted to investigate the mechanical properties of the membrane in an assumed environment of an artificial kidney, with an applied pressure ranging from 10–500 mmHg. The simulation was done using COMSOL Multiphysics 5.1 under stationary study with the membrane having a variation of surface area. From simulation, the...
Thermal wind sensor has been used to measure wind speed and direction in high temperature due to its principle. In this paper, a novel structure is proposed. It consists of a silicon sensing substrate and a ceramic chip for packaging, in which the sensing chip with through silicon vias (TSV) is Cu-Sn eutectic bonded to the ceramic. This paper focuses on the thermal-mechanical reliability of the novel...
The effect has been examined of Cu-Filled TSV under thermal shock test. The mismatch in the coefficients of thermal expansion between Cu metal and Silicon generates the thermal mechanical stress. The stress plays critical effect on the performance of the device structure and generates cracks. The Cu metal volume increase and separate from Si matrix after thermal shock test. The Cu metal drift can...
Fan-out wafer level packaging (FO-WLP) technology has been developed to shrink package size, to accommodate increasing I/O densities and to provide better electrical performance. However, wafer warpage induced during the process poses a threat to the yielding and reliability. In this paper, the warpage evolution during the FO-WLP process was investigated by theoretical calculation and finite element...
This work proposes and describes in details a complete setup solution for testing of non-encapsulated electronic devices under mechanical stress. The equipment was implemented and calibrated to later use in electrical characterization of devices, such as MOSFETs and diodes under controlled mechanical stress. The semiconductor bending equipment allows the electrical characterization of devices using...
An analytical analysis of stress profile in cylindrical nanowires vertically grown on silicon (Si) substrate has been performed. Depending on the lattice-mismatch a tensile stress as high as 1GPa for TiO2 nanowires and a compressive stress of 900MPa for InP nanowires has been obtained. The angular component of stress remains small indicating the nanowires will not be twisted as a result of the substrate-induced...
The effect on the stress profile for more than one nanowire constituting a matrix has been analyzed. There from it has been made evident that substrate as well as process-induced stress, irrespective of its nature, within the basal plane of a single nanowire gets reduced in a cluster of closely packed nanowires.
Conventional reliability demonstration test based on statistical method is widely used in industry as it is simple and convenient to apply. But for the products with high reliability and long life, this test method fails to satisfy the demand for short cycle and low cost, and is liable to cause the phenomenon of over-test and short-test. This paper gives a step-stress accelerated sequential probability...
Through silicon via (TSV) technology has attracted much attention as a key method to realize chip stacking and interposers interconnected of 3D packaging. Due to the thermal load during fabrication and operation of TSV structure, the thermal stress will be produced owing to the structural material high CTE mismatch, which may lead to the failure of the TSV structure. In the case of uneven thermal...
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