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In this paper, the principle of normalized minimum-sum (NMS) polar decoding process is explored. It is demonstrated that with one properly chosen parameters for NMS algorithm, performances approach to that of the sum-product (SP) algorithm can be achieved. As well, the complexity reduction is realized by calculating a linear function instead of nonlinear function. Simulation results for successive...
This paper reports low bit-error-rate (BER) polar codes concatenated low density parity check (LDPC) codes for wireless communication systems. The LDPC code has been validated on the error correction capable to approaching the theoretical value. However, the BER performance of this code is still limited because of the effect of the error floor. Therefore, a concatenated coding scheme based on polar...
The 10Gbase-KR protocol is widely used to accomplish the high speed data conversion in the Ethernet area. This paper presents a design of the critical controller in the physical coding sublayer based on the 10Gbase-KR. In order to satisfy the demand of the high speed data conversion, the scrambler and descrambler are specially designed to work in a parallel mode. The post-synthesis simulation results...
In this paper, the principle of density evolution (DE) combined with the normalized minimum-sum (NMS) decoding process is explored. It is demonstrated that with one properly chosen parameters for NMS algorithm, then almost the same behaviour of sum-product (SP) algorithm is achieved. As well, the complexity reduction is realized by calculating a linear function instead of nonlinear function. Simulation...
The given paper presents a method for constructing a QC-LDPC code of shorter length by length adaption from a given QC-LDPC code of maximal length. The proposed method can be considered as a generalization of floor lifting. Making some offline calculation it is possible to construct a sequence of QC-LDPC codes with different circulant sizes generated from a single exponent matrix of QC-LDPC code which...
Recently, both polar codes and low-density parity-check (LDPC) codes have been adopted by 3GPP eMBB scenario. Since both codes exist in one system, it is natural to consider the concatenation scheme of them. In this paper, a merged belief propagation (BP) decoding algorithm for the concatenated codes of polar and LDPC codes is proposed. By jointing factor graphs, this merged algorithm is designed...
In this paper, we studied the irregular row weight problem of DVB-S2 LDPC short frame. This problem will cause the failure of decoding. Based on a special structure of check matrix address table, we have achieved a simple and common solution to the problem.
Subject. Decoding and decision making models, methods and algorithms for elementary signals of receiving devices of distributed control systems elements. Purpose. Development, research and realization of soft decoding and decision making method for elementary signals (channel symbols) within receiving devices of distributed control systems elements based on the fuzzy logic fundamentals and methods...
New Raptor codes, based on low rate low-density parity-check (LDPC) codes, are proposed for short message length over various channels. The proposed Raptor codes are obtained by pre-coding the information bits by low rate LDPC codes and utilizing a low constant average degree distribution with high intermediate symbol recovery rate (ISRR). Simulation results demonstrate that the proposed Raptor codes...
Spatially coupled (SC) low-density parity-check (LDPC) codes can achieve capacity approaching performance with low message recovery latency when using sliding window (SW) decoding. An SC-LDPC code constructed from a protograph can be generated by first coupling a chain of block protographs and then lifting the coupled protograph using permutation matrices. This paper introduces a systematic design...
In the paper, we will discuss the powerfull class of channel codes referred to as turbo codes. We commence with a brief discussion for MAP and log-MAP decoding algorithms. Then we work with proposed turbo decoding method, which is called as PL-log-MAP. Some numerical results and research experiments, such as simulation for bit error rate estimation and images transmission have been presented. It is...
Logical elements for translation lookaside buffers were designed with single-event compensations and simulated on the bulk 65-nm CMOS design rule. The effects of upsets and single-event transients under impacts of single nuclear particles on MOS logical elements were minimized by the hardening the design. The basis of the fault-tolerant design is the hardened main row elements of the common matrix...
In this letter, a new early termination method is proposed for Luby transform (LT) belief propagation (BP) decoder. The proposed method is decided whether BP decoder output converges to original data bits by observing only sign alterations of log-likelihood ratio (LLR) messages in BP decoder structure. Simulation results and complexity analyzes show that proposed method has low computational complexity...
Bit-patterned media recording (BPMR) has been developed into an aggressive technology for the next-generation of hard disc drives (HDDs), aiming to extend storage density as well as to integrate into an HDD [1].
In this paper, new constructions of variable-rate quasi-cyclic low-density parity-check (QC-LDPC) codes are proposed. The criteria which guarantee that a higher-rate QC-LDPC code can be obtained by adding column-blocks to or removing row-blocks from the parity-check matrix of a given lower-rate QC-LDPC code are derived. Based on these criteria, new families of variable-rate QC-LDPC codes can be constructed...
In this paper, we solve the optimizing problem of designing Low-Density Parity Check codes for two parallel erasure links based on the known SDP approach. We show that our reformulation is suitable for this optimizing problem. Our results show that the optimal rate code design problem is a good way and worth-mentioning tool. One can extend our work to the other area.
Braided convolutional codes (BCCs) are a class of spatially coupled turbo-like codes (SC-TCs) with excellent belief propagation (BP) thresholds. In this paper we analyze the performance of BCCs in the finite block-length regime. We derive the average weight enumerator function (WEF) and compute the union bound on the performance for the uncoupled BCC ensemble. Our results suggest that the union bound...
SoC (System on Chip) is the integration of heterogeneous components and each component can act as a bus master. Simultaneous requests from bus masters, for shared bus, pose a great challenge for on chip communication. Arbiter ease this challenge by deciding who to grant the bus for communication when simultaneous requests are made by bus masters. One of the technique that arbiter follows is the lottery...
In this work, we study data shaping codes for flash memory. We first review a recently proposed direct shaping code for SLC (one bit per cell) flash memory that reduces wear by minimizing the average fraction of programmed cells. Then we describe an adaptation of this algorithm that provides data shaping for MLC (two bits per cell) flash memory. It makes use of a page- dependent cost model and is...
Logical elements with Single-Event Transients Compensation were simulated on the base of the bulk 28-nm CMOS design rule. The result of an impact of a single nuclear particle on MOS logical gate is a noise pulse, being a single-event transient. The combinational logic of error decoder can prevent all noise pulse propagating through NAND and NOR gates for the output state null “0” of bits error decoder...
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