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A novel and simple structure for improving CMRR is introduced. This structure can be added to the circuits like folded cascode amplifier, telescopic amplifier, current buffers, .etc to improve the CMRR of these circuits. This simple and effective circuit uses common mode deviating technique to improve CMRR at least 12dB while preserves CMRR bandwidth which is a novel technique in order to improve...
A CMOS receiver for optical wireless communication is presented. A stable feedback transimpedance amplifier (TIA) is designed adopting a current-mode amplifier as its feedforward gain element. A band-pass limiting amplifier is employed to boost the outputs of the receiver front-end. Implemented in a 0.35 um CMOS, the optical wireless receiver achieves a maximum transimpedance gain of 95.9 dBΩ. The...
This paper presents a wide intermediate-frequency (IF) bandwidth down-conversion double-balanced Gilbert-cell mixer design in a 0.13-μm CMOS process. The load stage of the mixer is implemented by an LC tank with switched capacitors to complete three selectable sub-bands to cover the desired wide IF band. Both the RF and LO ports are integrated with Marchand baluns for single-phase input consideration...
This paper presents a high-throughput deblocking filter accelerator which can process one macro block (MB) within 48 cycles for H.264/AVC/SVC. This innovation is achieved by considering both luminance and chrominance data together in arranging the filtering schedule. Cooperating with the filtering schedule, the proposed quadruple-filter-based architecture can simultaneously execute filtering of four...
In this paper, we propose a novel unipolar CMOS device with embedded oxide. Good inverter and logic gate output waveforms and behaviors are obtained. Utilizing the punch through effect, the Non-Classical Unipolar CMOS is demonstrated to enhance the tPLH so that the average delay time can be improved 23% when compared with the conventional CMOS. Due to all NMOS structures are only exploited and the...
In this paper the design and implementation of a delay-locked loop based temperature compensated MEMS clock is presented. The system is providing a temperature compensated 48 MHz clock signal for the range of - 40 to 85°C. The temperature compensation is achieved by a combination of initial and an autonomous background calibration. The main design guidelines have been on high integration level and...
This paper describes a digital-to-time converter (DTC) architecture that can be used as a fine interpolator in a time-to-digital converter (TDC) or as an adjustable delay in clock deskewing, for example. The new architecture of the DTC achieves adjustable sub-ps-level resolution with high linearity in ns-level dynamic range. The propagation delay adjustment is implemented by digitally controlling...
In this paper, an 8-bit (with 5-8bit mode selection), 440-MS/s pipelined Analog-to-Digital Converter (ADC) is presented. The ADC utilizes double-sampling in order to relax the operational amplifier (opamp) settling time requirements. Redundant sign digit (RSD) correction compensates offset errors of the comparators. The ADC is designed with a 0.13-μm CMOS process. In the 8-bit mode, measured effective...
This paper demonstrates how micromechanical on-chip MEMS resonators can be used as higher-order mixer-filters in RF front-end WSN nodes. Vibrating FFSFRs (Free-free Square Frame Resonator) connected together can create 4th and 6th order mixer-filter responses. The output is further enhanced by an on-chip amplifier, thus reducing stray capacitances. These mixer-filters are fabricated utilizing a CMOS-MEMS...
The influence of CMOS scaling on A/D-converter performance is investigated by observing the entire body of experimental CMOS ADCs reported in IEEE journals and conferences central to the field from 1976 to 2010. Based on the near-exhaustive set of scientific data, empirically observed scaling trends are derived for performance in terms of noisefloor, speed and resolution, as well as for power efficiency...
This paper presents a wideband inductorless Low Noise Amplifier (LNA) using a technique for canceling 2nd and 3rd order intermodulation products at the same time and hence achieving high second and third order Input Intercept Point (IIP2 and IIP3) at RF and microwave frequencies. The LNA also makes use of noise canceling stage to achieve low noise characteristics and low noise figure in the whole...
A DC-invariant gain control technique is introduced for differential CMOS variable-gain low-noise amplifiers (VG-LNA). Such technique provides an advantage of invariant DC bias current when the RF power gain is tuned over the gain control range. Therefore, the transconductance of NMOS transistor is unchanged, which minimizes the input match detuning. Consequently, the optimal design for noise, gain...
Silicon-controlled rectifier (SCR) has been reported with the good electrostatic discharge (ESD) robustness under the lower parasitic capacitance among ESD devices in CMOS technology. To correctly predict the performances of SCR-based ESD-protected RF circuit, it is essential for RF circuit design with accurate model of SCR device. The small-signal model of SCR in RF frequency band is proposed in...
Here we present the design and implementation of a 130-MHz on-chip reference oscillator in a 0.18-μm 1-ploy 6-metal digital CMOS process. To compensate for the influences on the oscillation frequency by process, supply voltage and temperature (PVT) variations, the oscillator uses a bias adjustment technique without BJT devices, on-chip inductors or external components. Measurements of 8 samples in...
This study proposes an approach to estimate parasitic capacitance shift under mechanical stress. The silicon-on-insulator n-/p-metal-oxide-semiconductor field-effect transistors (MOSFETs) and CMOS ring oscillators (ROs) were fabricated side by side in this study. External compressive stresses were applied on a <;110> strained channel of n-/p-MOSFETs and ROs in longitudinal and transverse configurations...
In this paper, an 1-bit second-order low-power ΔΣ modulator for pressure sensor applications is presented. The modulator utilizes correlated double-sampling (CDS) in order to reduce the flicker (1/f) noise. Due to the 1-bit output, the feedback DAC is inherently linear. The modulator is designed with 0.35-μm CMOS process. Measured signal-to-noise and distortion ratio (SNDR) is 86dB (14bits), while...
This paper deals with the design of CMOS sampling switch for ultra-low power analog-to-digital converters (ADC) in biomedical applications. General switch design constraints are analyzed, among which the voltage droop due to the subthreshold leakage current constitutes the major error source for low-speed sampling circuits. Based on the analyses, a CMOS sampling switch with leakage-reduction has been...
We present a non-traditional CMOS inverter composed a junctionless (JL) NMOSFET and an N+-N--P transistor which with simple process and high integration density in this paper. In the non-traditional CMOS inverter the JL NMOSFET serves as driver and the N+-N--P transistor serves as load, respectively. Based on the measurement date of the N+-N--P transistor published, we draw the load line of the non-traditional...
In this study, we introduce a far field-aware system on a chip (SOC) design for sound source location, which is implemented with 0.18-μm CMOS process. The adopted method for the proposed system is based on average magnitude difference function (AMDF). In order to effectively detect the acoustical source in actual environment, we integrate this system with voice active detection (VAD), which can actively...
This paper presents a practical phase noise measurement approach, which only requires a spectrum analyzer and a computer, featuring fast setups, accurate results and low cost. Not like the conventional methods using extra assistant circuits to get rid of the frequency drift problem, this approach takes advantage of modern spectrum analyzers to acquire IQ data to calculate phase noise. The low quantization...
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