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Stencil computation is one of the important kernels in scientific computations, however, the sustained performance is limited by memory bandwidth especially on multi-core microprocessors and GPGPUs due to its small operationalintensity. In this paper, we propose a scalable streaming-array (SSA) of simple soft-processors for high-performance stencil computation on multiple FPGAs. The SSA architecture...
In state-of-the-art multi-processor systems-on-chip (MPSoC), interconnect of processing elements has a major impact on the system's overall average-case and worst-case performance. Moreover, in real-time applications predictability of inter-chip communication latency is imperative for bounding the response time of the overall system. In shared-memory MPSoCs buses are still the prevalent means of on-chip...
The SHA-3 competition organized by NIST has triggered significant efforts in performance evaluation of cryptographic hardware and software. These benchmarks are used to compare the implementation efficiency of competing hash candidates. However, such benchmarks test the algorithm in an ideal setting, and they ignore the effects of system integration. In this contribution, we analyze the performance...
This paper presents a scalable and flexible multi-core SoC architecture for high-speed key exchange for emerging IP security systems. Novel approaches are proposed for HMAC authentication block parallelization, distributed key handling and a pipelined block cipher design that allows feedback encryption modes. This improves upon previous state-of-the-art designs for IPSec, creating an architecture...
MPI is the traditional paradigm to parallelize applications for High Performance Computing environments. AzequiaMPI is an implementation of the MPI-1.3 standard. Its thread-based architecture enables it to run on high-end HPC machines as well as on embedded environments as soft-core processor in FPGAs. This article describes the experience of building a maintainable cluster of fourteen popular Xilinx...
This paper presents a design of a kind of high speed image acquisition card based on PCI Express bus. The program uses FPGA to decode Cameralink image data, using on-chip resources to achieve the FIFO and off-chip SDRAM control logic, making a high-speed connection with the host pc through the PEX8311 based on PCI EXPRESS bus. After testing, the speed is satisfying the needs of high- speed raw image...
This paper presents three reconfigurable radio systems developed within CTVR, The Telecommunications Research Centre and demonstrated at the IEEE International Dynamic Spectrum Access Networks (DySPAN) symposium held in Chicago in October 2008. All three systems were developed using the Iris cognitive radio network architecture. Each system employs a different processing platform. Today's radio communication...
The Reconfigurable Computing Cluster Project at the University of North Carolina at Charlotte is investigating the feasibility of using FPGAs as compute nodes to scale to PetaFLOP computing. To date the Spirit cluster, consisting of 64 FPGAs, has been assembled for the initial analysis. One important question is how to efficiently communicate among compute cores on-chip as well as between nodes. Tight...
Platform FPGAs are capable of hosting entire Linux- based systems including standard peripherals, integrated network interface cards and even disk controllers on a single chip. Filesystems, however, are typically implemented in software as part of the operating system. This presents a challenge as some applications are very sensitive to file I/O latency and Platform FPGA processor cores are clocked...
FPGAs are becoming an attractive platform for accelerating many computations including scientific applications. However, their adoption has been limited by the large development cost and short life span of FPGA designs. We believe that FPGA-based scientific computation would become far more practical if there were hardware libraries that were portable to any FPGA with performance that could scale...
The purpose of TAFT fault tolerance studies conducted at CNES is to prepare the space community for the significant evolution linked to the usage of COTS components for developing spacecraft supercomputers. CNES has patented the DMT and DT2 fault-tolerant architectures with 'light' features. The development of a DMT/DT2 testbench based on a PowerPC7448 microprocessor from e2v is presented in this...
The possibility to adapt in-flight the behaviour of a space-based equipment to different operating conditions and/or new functional requirements is of paramount importance in the field of the commercial multimedia communications. In fact, in a satellite lifetime of 15 years, new standards may arise, the existing one may be upgraded, or the opportunity to introduce new added-value services may be considered...
This paper describes prototype implementations of single-chip multiprocessor systems with a configurable router intended for dedicated, embedded network-on-chip support within field-programmable gate arrays in order to provide performance and flexibility for system-on-chip applications. The router supports ring, octagon, and mesh network topologies. Implementation in an Altera Stratix EP1S80 chip...
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