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Search RSS2015 interdyscyplinarne centrum modelowania matematycznego i komputerowego60Device-Circuit Interactions and Impact on TFT Circuit-System Design
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This paper reviews the importance of device-circuit interactions (DCI) and its consideration when designing thin film transistor circuits and systems. We examine temperature- and process-induced variations and propose a way to evaluate the maximum achievable intrinsic performance of the TFT. This is aimed at determining when DCI becomes crucial for a specific application. Compensation methods are then reviewed to show examples of how DCI is considered in the design of AMOLED displays. Other designs such as analog front-end and image sensors are also discussed, where alternate circuits should be designed to overcome the limitations of the intrinsic device properties./resource/bwmeta1.element.ieee-art-000007739990Tunnel FETs for Ultralow Voltage Digital VLSI Circuits: Part I—Device–Circuit Interaction and Evaluation at Device Level
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This paper and the companion work present the results of a comparative study between the tunnel-FETs (TFETs) and conventional MOSFETs for ultralow power digital circuits targeting a <inline-formula> <tex-math notation="LaTeX">$V_{\rm{DD}}$ </tex-math></inline-formula> below 500 mV. For this purpose, we employed numerical TCAD simulations, as well as mixed device–circuit and lookup-table simulations using either the SENTAURUS or the Verilog-A environment. In particular, in this paper, we explore the device–circuit interaction in n- and p-type TFETs, and propose a design leading to a good tradeoff between the current leakage and transistor imbalance at ultralow <inline-formula> <tex-math notation="LaTeX">$V_{\rm{DD}}$ </tex-math></inline-formula>, as required in ultralow voltage systems. Then, we systematically compare the <inline-formula> <tex-math notation="LaTeX">$I_{{{\rm OFF}}}$ </tex-math></inline-formula>, <inline-formula> <tex-math notation="LaTeX">$I_{{{\rm ON}}}$ </tex-math></inline-formula>, effective capacitance, OFF-state and ON-state stacking factors for TFETs, SOI, and bulk MOSFETs in a wide range of <inline-formula> <tex-math notation="LaTeX">$V_{\rm{DD}}$ </tex-math></inline-formula>. These results allow us to infer preliminary indications about the amenability for an aggressive voltage scaling of TFETs compared with MOSFETs, which will be further developed in the companion paper. We also report simulation results for the sensitivity of the transistors to the variation of some key device parameters. Even these process variation results set the stage for a more thorough investigation addressed in the companion paper about the limits imposed by process variability to voltage scaling for either TFETs or MOSFETs circuits./resource/bwmeta1.element.ieee-art-000006748988Mixed-Mode Simulation of Nanowire Ge/GaAs Heterojunction Tunneling Field-Effect Transistor for Circuit Applications
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In this paper, a nanowire germanium/gallium arsenide (Ge/GaAs) heterojunction-based tunneling field-effect transistor (TFET) is investigated, with an emphasis on the device-circuit interaction. It is applied to a common-source (CS) amplifier, one of the most fundamental analog circuit blocks, and its performance is evaluated with a device-circuit mixed-mode simulation. Furthermore, the passive elements are adjusted to obtain the proper operating point (<formula formulatype="inline"><tex Notation="TeX">$Q$</tex></formula>-point) of the circuit, and high-frequency operations are evaluated on this basis. Moreover, from the simulation results, the transfer function is successfully modeled and verified, which shows that the CS amplifier with the heterojunction TFET works as a single-zero and two-pole system. The 3-dB roll-off and unity-gain frequencies are 320 GHz and 2 THz, respectively, which is evidence for circuit applications in the extremely high-frequency regime./resource/bwmeta1.element.ieee-art-000006492093