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To maintain Moore’s law, the semiconductor industry decided a decade ago that a new transistor was imperative. That silver bullet has yet to materialize, but computer design innovations are now maintaining or even exceeding expected scaling progress. This theme issue gives a cross-sectional view of these new scaling drivers.
Decades-old explicit dataflow architectures eliminate many of the overheads of general-purpose processors but have not been successful because of their lack of sufficient control speculation and the latency overhead of explicit communication. This article observes a synergy between out-of-order (OoO) and explicit dataflow processors, in which dynamically switching between them according to program...
An extension to the classic von Neumann paradigms is suggested, which -from the point of view of chip designers- considers modern many-core processors, and -from the point of view of programmers- still remains the classic von Neumann programming model. The work is based on the ideas that 1) the order in which the instructions (and/or code blocks) are executed does not matter, if some constraints do...
The issues of memory latency, synchronization, and distribution costs in multiprocessors are reviewed. The approaches taken by conventional and data flow architectures are contrasted in relation to these issues. It is pointed out that each approach fits well for a certain situation and that it is possible to have a common framework in which the two execution models can be mixed to suit the situation...
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