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Power and energy consumption are seen of one of the most critical design factor for any next generation large-scale HPC system. The price centers have to pay for energy is shifting the budgets from investment to operating costs, leading to scenarios in which the sizes of systems will be determined by their power needs, rather by the initial hardware cost. As a consequence, virtually all funding agencies...
The current design drivers for multi-cores, namely performance per watt, scalability and flexibility, make the Networks-on-Chip (NoCs) the de-facto on-chip interconnect. State of the art NoCs can exploit heterogeneous solutions and complex DVFS techniques to fulfill also the variability of the application requirements. Relevant showstoppers to the design of a truly flexible NoC fitting all the possible...
Energy efficiency of servers has become a significant issue over the last years. Load distribution plays a crucial role in the improvement of energy efficiency as (un-)balancing strategies can be leveraged to distribute load over one or multiple systems in a way in which resources are utilized at high performance, yet low overall power consumption. This can be achieved on multiple levels, from load...
The traditional low-power embedded processors such as ARM and Atom are entering the high-performance server market. At the same time, big data analytics are emerging and dramatically changing the landscape of data center workloads. Thus, the question of whether low-power embedded architectures are suited to process big data applications efficiently, is becoming important. In this work, through methodical...
JavaScript is the most widely used web programming language and is increasingly used to implement sophisticated and demanding applications in such domains as graphics, games, video, and cryptography. The performance and energy usage of these applications can benefit from hardware parallelism, including SIMD (Single Instruction, Multiple Data) vector parallel instructions. JavaScript's current support...
Optimizing the power-performance tradeoff of a software system is challenging as the design space is large and live data is difficult to obtain. As a result, many power reduction techniques are based on power models which may not represent the full complexity of the system being analyzed. In this paper, in contrast, we propose a process for performing a tradeoff analysis using live power/performance...
We propose memory-aware VM consolidation to achieve energy-efficiency of a data center while enhancing performance of VMs. Consolidation without awareness of the memory-access demand can cause inefficient resource utilization and degrade system performance. In this chapter, we propose efficient consolidation of VMs based on the memory-access demand of these VMs to improve overall system performance...
Worst case execution time (WCET) analysis is used to verify that real-time tasks on systems can be executed without violating any timing constraints. Power consumption is not considered in most of the WCET research work. However, real-time embedded systems have limited power resources and the leakage power cost by the cache could take up to 40% of the total power consumption. Because of the nature...
Accelerators are used in about 13% of the current Top500 List. Supercomputers leveraging accelerators grew by a factor of 2.2x in 2012 and are expected to completely dominate the Top500 by 2015. Though most of these deployments use NVIDIA GPGPU accelerators, Intel's Xeon Phi architecture will likely grow in popularity in the coming years. Unfortunately, there are few studies analyzing the performance...
In recent years, multiple Voltage Frequency Island (VFI)-based designs have increasingly made their way into both commercial and research multicore platforms. On the other hand, the wireless Network-on-Chip (WiNoC) architecture has emerged as an energy-efficient and high bandwidth communication backbone for massively integrated multicore platforms. It becomes therefore possible to exploit the small-world...
The need for fast address translation within tight time constraints (before L1 tag check but after effective address computation) imposes many design constraints. The freedom from such constraints can potentially lead to lower TLB energy costs. In this paper, we observe that (1) data accesses commonly use base-displacement addressing modes in which the effective address is computed as the sum of a...
Cloud computing is a consolidation environment that hosts heterogeneous applications. Currently, clouds use virtualization technologies to provide an isolated execution environment and agile resource provisioning. Furthermore, live migration is widely exploited to achieve energy saving. However, consolidation and live migration can cause resource contention and utilization overhead that influence...
A key question for the microprocessor research and design community is whether scaling multicores will provide the performance and value needed to scale down many more technology generations. To provide a quantitative answer to this question, a comprehensive study that projects the speedup potential of future multicores and examines the underutilization of integration capacity—dark silicon—is...
Systematically exploring power, performance, and energy sheds new light on the clash of two trends that unfolded over the past decade: the rise of parallel processors in response to technology constraints on power, clock speed, and wire delay; and the rise of managed high-level, portable programming languages.
Power management is one of the biggest challenges facing current data centers. As processors consume the dominant amount of power in computer systems, power management of multicore processors is extremely significant. An efficient power model that accurately predict the power consumption of a processor is required to develop effective power management techniques. However, this challenge rises with...
As the VLSI technology advances into the deep submicron era, power consumption becomes a critical issue for designing a high performance chip. Voltage-island design methodology based on multiple supplying voltages is one of efficient ways to reduce overall power consumption. This work proposes an algorithm to complete an X-clock tree that connects several voltage-islands. We first construct the X-clock...
Micro-channel cooling shows great potential in removing high density heat in 3D circuits. The current micro-channel heat sink designs spread the entire surface to be cooled with micro-channels. This approach, though might provide sufficient cooling, requires quite high pumping power. In this paper, we investigate the non-uniform allocation of micro-channels to provide sufficient cooling with less...
As the system scales up continuously, the problem of power consumption for high performance computing (HPC) system becomes more severe. Heterogeneous system integrating two or more kinds of processors, could be better adapted to heterogeneity in applications and provide much higher energy efficiency in theory. Many studies have shown heterogeneous system is preferable on energy consumption to homogeneous...
As one of the most popular many-core architecture, GPUs have illustrated power in many non-graphic applications. Traditional general purpose computing systems tend to integrate GPU as the co-processor to accelerate parallel computing tasks. Meanwhile, GPUs also result in high power consumption, which accounts for a large proportion of the total system power consumption. In this paper, we mainly focus...
Implants are nowadays transforming rapidly from rigid, custom-based devices with very narrow applications to highly constrained albeit multifunctional embedded systems. These systems contain cores able to execute software programs so as to allow for increased application versatility. In response to this trend, a new collection of benchmark programs for guiding the design of implant processors, ImpBench,...
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