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This paper presents how the throughput of a server is influenced by the applying a vertical scalability. The paper studies the results obtained in measuring the response time of the server and the processing time of the server when dealing with a large number of requests by modifying the configuration of the machine, increasing the number of cores the machine has and increasing the RAM capacity. This...
This paper presents the development of next generation e-learning systems for real-time video, voice conferencing and streaming technology over secure socket layer (SSL) IPv6 in campus environment. Development of the V2oIP e-learning systems has contributed a significant value to distance learning. The aim of this study is to design real time interactive learning systems with security over SSL IPv6...
In this paper, we define analytically a mathematical model of a VoIP Server, or more precisely the Asterisk server from the search results of Eduardo and Pablo Montoro casilari. From these models we verified the similarity of results from the outcome of the experiment cited above. Our theme therefore focuses on using material: RAM, CPU and bandwidth of a VoIP Server with respect to the number of calls...
Deduplication has been widely used in disk-based secondary storage systems to improve space efficiency. However, there are two challenges facing scalable high-throughput deduplication storage. The first is the duplicate-lookup disk bottleneck due to the large size of data index that usually exceeds the available RAM space, which limits the deduplication throughput. The second is the storage node island...
In this paper, they address a key challenge for scaling image search up to larger databases: the amount of memory consumed by the inverted index. In a VT-based image retrieval system, the most memory-intensive structure is the inverted index. For example, in a database of one million images where each image contains hundreds of features, the inverted index consumes 2.5 GB of RAM. Such large memory...
Most existing approaches to targeting high-level software to FPGAs are based on extensions to C and do not map easily to the features and characteristics of modern FPGAs. These include massive parallelism and a variety of complex IP-blocks (eg. RAMs, DSPs). In this paper we discuss a hardware implementation of SR, a software language with first class concurrency and high-level IPC.We show that the...
In this paper, we propose and demonstrate a novel wireless camera network system, called CITRIC. The core component of this system is a new hardware platform that integrates a camera, a frequency-scalable (up to 624 MHz) CPU, 16MB FLASH, and 64MB RAM onto a single device. The device then connects with a standard sensor network mote to form a camera mote. The design enables in-network processing of...
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