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With worldwide communication of the private and confidential data over the computing networks or internet, there is always a chance of threat of data confidentality, data integrity and also of data availability. Information has become one of the most important assests in growing demand of need to store every single importance of events in everyday of our life. Encipherment is one of the important...
Advanced Encryption Standard (AES) is the most widely used public cipher algorithm for crypto related applications in embedded systems. This paper presents an area efficient 16-bit AES architecture for key expansion, encryption and decryption. In the proposed design, a modular approach is adopted and it is capable of performing all transformations for 128, 192 and 256-bit cipher key lengths. The resources...
The Advanced Encryption Standard (AES) is the main algorithm used to ensure security and privacy in several different applications ranging from massive data servers to small low-power embedded systems. Such embedded systems often rely on dedicated hardware implementations of AES in order to meet tight power budgets. In this scenario, C/C++ High-Level Synthesis (HLS) solutions are gaining acceptance...
In the paper, the structure of information security system was implemented and to evaluate its performance for the securely data transmit in the network. The Advanced Encryption Standard (AES) with Rijndael algorithm is divided into two major block encryption and decryption which is operated for the iteration and the symmetric password key block cryptography with 128, 196, and 256-bit. The Content...
This paper presents high speed architecture for AES encryption. The proposed architecture uses integrated unit of encryption in which the consecutive transformations of AES are integrated into a single unit to arrive at an architecture with shorter critical path. Further reduction in critical path is achieved by applying pre-computation technique. Synthesis results using Synopsis 0.18 μιη CMOS process...
This paper presents a half-run RC5 cipher architecture with low power dissipation for transmission security of biomedical systems. The proposed architecture uses a resource-sharing approach utilizing only one adder/subtractor, one bi-directional barrel shifter, and one XOR with 32-bit bus width. Therefore, two data paths are switched through four multiplexers in the encryption/decryption procedure...
The Active Network is a new type network architecture which intermediate node could be programmed. However, its architecture feature bring many security problems which embarrassed the development of active network greatly. This context analyze and studies the characteristics of active network communication and the security problems exist in the process. At the same time, we put forward a safe communication...
Advance Encryption Standard (AES), has received significant interest over the past decade due to its performance and security level. In this paper, we propose a compact 8-bit AES crypto-processor for area constrained and low power applications where both encryption and decryption is needed. The cycle count of the design is the least among previously reported 8-bit AES architectures and the throughput...
Secure Multi-Party Computation (SMC) allows parties with similar background to compute results upon their private data, minimizing the threat of disclosure. The exponential increase in sensitive data that needs to be passed upon networked computers and the stupendous growth of internet has precipitated vast opportunities for cooperative computation, where parties come together to facilitate computations...
This paper proposes a high-throughput cost-effective implementation of AES supporting encryption and decryption with 128-, 192-, and 256-bit cipher key. Optimum irreducible polynomial coefficients are selected to construct the composite field GF(((22)2)2) on standard and normal base in order to minimize the gate count in SubBytes/InvSubBytes transformation. In addition, MixCoulmn/InvMixColumn transformations...
This paper presents the implementation of a tightly coupled hardware architectural enhancement to the Altera FPGA-based Nios II embedded processor. The goal is to accelerate Advanced Encryption Standard (AES) operations in 128, 192 and 256-bits, for application in a high-performance embedded system implementing symmetric key cryptography. The concept is to augment the embedded processor with a new...
This paper proposes an ASIC implementation of a chaos-based image encryption algorithm, which features dual-RAM connection and reusable data-path for each round of encryption and decryption. Within a pixel block, general cat-map and logistic map are alternately used for permutation, diffusion and substitution. The algorithm is robust to many forms of attacks, and the proposed hardware structure bears...
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