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Device, interconnect scaling and interconnection bottleneck are among the major challenges for CMOS scaling. Furhtermore, signal integrity issues like crosstalk-leakage of charge between capacitively coupled nets among neighboring signal lines-is becoming inexorable. We propose to astutely turn this detrimental effect into an advantage by engineering the interference among signal lines. Our proposal...
Interconnect opens are known to be one of the predominant defects in nanoscale technologies. Automatic test pattern generation for open faults is challenging, because of their rather unstable behavior and the numerous electrical parameters which need to be considered. Thus, most approaches try to avoid accurate modeling of all constraints like the influence of the aggressors on the open net and use...
The feasibility of flipflop designs for storing hexadecimal datum is studied in this work. Hexadecimal signal processing appears the benefit on the great reduction of interconnections, which leads to the potential of improving various performances. However, the storage of hexadecimal datum is very challenging for the conventional binary implementations. In this paper, a prototype of hexadecimal flipflop...
Interconnect opens are a major class of defects found in today’s nanometer technologies. These defects present subtle behavior that could lead to test escapes and hence compromise test quality. Furthermore, they could become a reliability risk. Low-voltage testing has been suggested as a static test to improve the defect coverage of interconnect opens. In nanometer technologies, process variability...
Interconnect opens are known to be one of the predominant defects in nanoscale technologies. Generating tests to detect such defects is challenging due to the need to accurately determine the coupling capacitances between the open net and its aggressors and fix the state of these aggressors during test. Process variations cause deviations from assumed values of circuit parameters thus potentially...
Open defects such as interconnect opens are known to be one of the predominant defects in nanoscale technologies. Yet, test pattern generation for open defects is challenging because of the high number of parameters which need to be considered. Additionally, the assumed values of these parameters may vary due to process variations reducing fault coverage of a test set generated under this assumption...
Interconnect opens are known to be one of the predominant defects in nanoscale technologies. However, automatic test pattern generation for open faults is challenging, because of their rather unstable behaviour and the numerous electric parameters which need to be considered. Thus, most approaches try to avoid accurate modeling of all constraints and use simplified fault models in order to detect...
The FinFET technology is considered as the best candidate to extend the CMOS technology down to 10 nm. In this paper, a three-dimensional (3-D) parasitic extraction flow is proposed for modeling and timing analysis of the FinFET based circuits. The flow fully considers the 3-D geometry of the FinFET and employs accurate field solvers for extracting resistances and capacitances. Thus, it accurately...
CMOS IC scaling has provided significant improvements in electronic circuit performance. Advances in test methodologies to deal with new failure mechanisms and nanometer issues are required. Interconnect opens are an important defect mechanism that requires detailed knowledge of its physical properties. In nanometer process, variability is predominant and considering only nominal value of parameters...
Double-patterning lithography is a choice for critical layers in 32 nm and 22 nm technologies. Double patterning lithography techniques require additional masks to manufacture a single device layer. Consequently, double-patterning lithography brings overlay as a challenge that introduces additional variability to gate coupling capacitances. This additional variability may negatively impact circuit...
In this paper, we present a new 3D wirelength distribution model which considers the contribution of through-silicon-via (TSV) on wirelength, die area, and power consumption. Since TSVs occupy the device layer together with active devices, the die area increases if TSVs are utilized. This area overhead, which in turn affects the wirelength, worsens due to the large size of TSVs themselves, which is...
This paper presents a methodology to accurately evaluate the input waveforms of CMOS gates for static timing analysis (STA) in the presence of crosstalk noise. Currently, gate delay is calculated by looking-up 2-dimension table using input waveform slope and gate load capacitance, and CMOS gate input waveforms are usually represented using the latest arrival time and transition time (slope) conventionally...
In this paper, we consider the problem of selecting a set of aggressor nets that maximize crosstalk induced noise or delay pushout on a coupled victim net, under given logical constraints. We formulate the problem mathematically, and propose efficient Lagrangian Relaxation and network flow based approaches that guarantee an optimal solution. We also formulate and solve this problem while considering...
In this paper, we present a new technique to improve the reliability of H-tree SRAM memories. This technique deals with the SRAM power-bus monitoring by using built-in current sensor (BICS) circuits that detect abnormal current dissipation in the memory power-bus. This abnormal current is the result of a single-event upset (SEU) in the memory and it is generated during the inversion of the state of...
Transient faults have become increasingly observable in combinational logic. This is due to the weakening of some inherent protective mechanisms that logic traditionally holds against such flawed spurious events. One of the aforementioned mechanisms relates to the propagation of transient faults along sensitizable paths. Existing literature that relies on logic simulation under estimates the number...
This paper proposes a new approach to analyze crosstalk of coupled interconnects in the presence of process variations. The suggested method translates correlated process variations into orthogonal random variables by principle component analysis (PCA). combined with polynomial chaos expression (PCE), the technique utilizes Stochastic Collocation Method (SCM) to analyze the system response of coupled...
A novel methodology for accurate and efficient static timing analysis is presented in this paper. The methodology is based on finding a frequency domain model for the gates which allows uniform treatment of the gates and interconnects. It is shown that despite the highly nonlinear overall gate model, a frequency domain model of the gate with the model parameters, gate moments, as functions of the...
The power consumption and the matching will be the principal issues at the 32 nm node and below. In this context, Ultra-Thin Body devices are extensively studied for the end-of-roadmap CMOS. In this paper we present the SON technology, leading to the simple fabrication of sustained mono-Si nano-membranes over an empty tunnel, and discuss on the application of this process to build-up electronic devices...
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
3D contactless technology based on capacitive coupling represents a promising solution for high-speed and low power signaling in vertically integrated chips. AC coupled interconnects do not suffer from mechanical stress, and the parasitic load is much reduced when compared to standard DC solutions, such as wire bonding and micro bumps. Communication system based on wireless interconnection scheme...
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