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The detection of the fundamental frequency and phase angle of the positive sequence grid voltages are utmost necessary for the proper operation of controlled active power converters, which require to operate stable and robust even during the presence of diverse power quality issues. There exist various utility grid synchronization and detection methods based on Phased-Locked Loop (PLL) techniques...
This paper presents the design for a prototype tactical dynamic spectrum access (DSA) mobile ad hoc network, where the network is organized into clusters operating on a single frequency. The frequency may be changed autonomously by the network in response to jamming or interference, after some frequency switching delay. The network node design is implementable on a software defined radio (SDR), such...
This paper presents an efficient design method used to implement high performance multi-mode memory controllers which fits different applications with different demands. The proposed design method is based on the use of dynamic partial reconfiguration (DPR) to commute from mode to another using time-multiplexing on the same chip region to save considerable area and enable usage of low-cost FPGAs....
As fault-tolerant Networks-on-Chip (NoCs) become prevalent in reliable systems, their overhead must be accurately evaluated. In this paper, we evaluate the overhead of a soft error resilient real-time NoC router for ASICs in terms of area and power. We employ a power analysis framework and load profiles that provide accurate power figures. Furthermore, we analyze the power behavior in normal operation...
Bufferless, deflection-routed, Butterfly Fat Trees (BFTs) can outperform state-of-the-art FPGAs overlay NoCs such as Hoplite by as much as 2–5× on throughput and ≈5× on worst-case latency at identical PE counts, and by ≈1.5× on throughput at identical resource costs >16K LUTs for statistical traffic patterns. In this paper, we show how to modify the tree connectivity and routing function to support...
A new power estimation approach based on the decomposition of a digital system into basic operators is presented. This approach aims to estimate the energy consumption at early design phases of digital blocks implemented on FPGAs. Each operator has its own model which estimates the switching activity and the power consumption. By interconnecting several operators, statistical information is then propagated...
The most common error mitigation scheme used for hardening designs against radiation-induced upsets on FPGAs is Triple Modular Redundancy (TMR). In a TMR system, there are three copies of a module and voting circuits that mask errors by voting for the majority. There are several types of voting circuits which can be classified based on their insertion sites in the design, functionality or the type...
Deflection-routed FPGA overlay NoCs such as Hoplite suffer from high worst-case routing latencies due to the penalty of deflections at large system sizes. Segmentation of communication channels in such NoCs can (1) reduce worst-case packet routing latencies for FPGA traffic, (2) enable efficient composition of multi-application NoC workloads, and (3) ease the burden of supporting Partial Reconfiguration...
Accelerator-in-Switch (AiS) is a framework for building an accelerator logic tightly coupled with a switching hub in a single FPGA for high performance computation with heterogeneous environment with CPUs and GPUs. AiS is implemented on a partial reconfigurable region of an FPGA whose permanent region is used for a switching hub. A port of the switching hub is connected to the registers and local...
High switching frequencies(>1 MHz) become available due to the development of wide bandgap semiconductors. This trend of increasing operating frequency in power electronics results in the reduction of output filter sizes and costs. As frequency increases, parasitic behavior of components become more dominant. This paper shows the possibility to shift the generated EMI peaks to the most effective...
Image-guided high intensity focused ultrasound (HIFU) is widely used not only for non-invasive therapy but also as a precise approach for cardiac tissue ablation. However, most HIFU systems use piezoelectric transducers, which are typically bulky due to active cooling, and separate imaging and HIFU transducers, and therefore impractical for catheter-based applications. Taking advantage of a single...
In this paper, a high performance fully digital peak current mode controller for DC-DC converters which supports the full duty cycle range from 0–100% is presented. Support for low duty cycle is very important during short circuit or converter overload and support for high duty cycle is important for faster response during a transient and for providing a larger output voltage range. The digital current...
Modern semiconductor chips offer a FPGA, A Hard Microcontroller and a programmable Analog circuitry all integrated on a single chip, which gives the system designer a full featured, easy-to-use design and development platform where all the units are programmable and under full control of the designer, Combining this state of the art silicon chip with a Real Time Operating Systems (RTOS) gives an Engineer...
This article shares experience and lessons learned in teaching course on programmable logic design at Universitas Muhammadiyah Surakarta, Indonesia. This course is part of bachelor of engineering (electrical) degree program. Project-based approach is chosen to strengthen these students' understanding and practical skills. Each year's project involves challenges for the students to solve by implementing...
Hierarchical routing resources play vital role in FPGA routing. Better routability options can be obtained using segmented approach of wires thus enabling routing optimization. Source and sink logic blocks can be connected via wire segments such that the overall wire length and switching transistors inside the switch box can be saved over an extent. This paper presents an experimental approach of...
This paper presents a random space vector pulse width modulation (SVPWM) strategy for a three-phase voltage source inverter based on Field Programmable Gate Array (FPGA). It is more flexible and faster to realize randomization algorithm in FPGA than digital signal processor (DSP). What's more, it is easily extensible for multiphase driving systems with FPGA. Models in Simulink and an experiment platform...
This paper presents an original and unique embedded FFT hardware algorithm development process based on a systematic and scalable procedure for generating permutation-based address patterns for any power-of-2 transform size algorithm and any folding factor in a Kronecker Pease FFT hardware implementation. This is coupled by a procedure to perform automatic code generation of Kronecker FFT cores. The...
In this paper, a novel way to finely tune a net delay on Xilinx Field Programmable Gate arrays (FPGAs) is proposed. It consists of adding floating interconnects (nodes) to the net on which the delay is to be tuned, connected to any input pin of a switch matrix along the net. Adding nodes is made with a TCL script applied to an already placed and routed design. However, such nodes, also called antennas,...
A promising technique to improve the performance per area factor for multithreaded soft-processors on FPGAs is System Hyper Pipelining (SHP), which can be efficiently applied on the register rich reconfigurable technologies with their distributed memory structures. SHP overcomes the limitations of C-Slow Retiming by adding context switching to enable thread stalling and thread bypassing possibilities...
Securely processing data in the cloud is still a difficult problem, even with homomorphic encryption and other privacy preserving schemes. Hardware solutions provide additional layers of security and greater performance over their software alternatives. However by definition the cloud should be flexible and adaptive, often viewed as abstracting services from products. By creating services reliant...
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