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We present a digital system for measurement of neutron spectra in mixed gamma-neutron fields. The signal from a standard scintillation detector is sampled at rate up to 1 GHz, using 12-bit analog-to-digital converters. First stage of the signal processing is performed on a Virtex 6 FPGA and partial results are streamed through a fast Ethernet link to a computer, where the final processing takes place...
Physical unclonable functions (PUFs) have become commercially available for anti-counterfeiting and authentication applications. PUF circuits are built on ASICs but can be implemented on FPGAs. For many electronic products, FPGAs are used in order to shorten development periods and reduce costs. Therefore, implementing PUFs on FPGAs can improve security in nearly all electronic products. However,...
This paper presents a kind of architecture design of bus based CNC system of domestic-processor based on Loongson and analyzes both the design of module structure of domestic-processor based on Loongson and the function and implementation method of MII bus based CNC main control board. These studies can solve the problem of chip of domestic NC system chip and have great significance to improve the...
Due to technology scaling, which means smaller transistor, lower voltage and more aggressive clock frequency, VLSI devices are becoming more susceptible against soft errors. Especially for those devices deployed in safety- and mission-critical applications, dependability and reliability are becoming increasingly important constraints during the development of system on/around them. Other phenomena...
This paper presents a Controller Area Network (CAN) communication system in the Field-Programmable Gate Array (FPGA), which is Xilinx Artix-7. Hardware circuits and the software flow char are described in detail. The reusable IP (Intellectual Property) technology is used in FPGA as the core controller. In addition, the CAN communication system is implemented by System-on-a-Programmable-Chip (SOPC)...
The parallelism of hardware and the dynamic reconfigurability of FPGAs enable multiple hardware tasks to run concurrently, and also time-share resources by being swapped in and out of the device during runtime. More than ever before, these capabilities are being employed in systems with high-reliability requirements. To improve reliability, a method often used is circuit relocation. However, the static...
In this paper, design of a novel Network on Chip (NoC) structure and its integration with Reliable Reconfigurable Real Time Operating System (R3TOS) are presented. NoC has been recently identified as a scalable communication paradigm to avoid the communication bottleneck in bus based communications. Dynamically Reconfigurable Field Programmable Gate Array (FPGA)s are particularly suited for applications...
A new real time control system is being installed on the Electron Cyclotron (EC) heating system at the DIII-D tokamak, which opens new possibilities for plasma experiments while increasing the gyrotron system reliability. The control system allows restarting the gyrotrons after an incipient fault is detected and cleared. The EC installation is being used for a wide variety of experiments requiring...
Hardware implementations of Object-Tracking Algorithms, like most integrated circuits, are susceptible to radiation-induced soft errors. This work evaluated the reliability of a field-programmable gate array (FPGA) prototype for object-tracking algorithms via fault emulation experiments conducted at the register-transfer level (RTL). Faults were injected into the main sub-modules within the object-tracking...
Silicon based Physical Unclonable Function (SPUF), a chip level identifier that utilizes the inherent irregular manufacturing process variations, can be extended to Ring Oscillator PUFs (ROPUFs). The ROPUF structure, although promising for FPGA based platforms, is not area efficient in terms of response bit per RO circuit implementation. This paper introduces an area efficient Stage Configurable ROPUF...
As the security is becoming more and more important these days, we still should not forget about reliability. When designing a cryptographic device for some mission-critical or another reliability demanding system, we need to make the device not only attack-resistant, but also fault-tolerant. There are many common fault-tolerant digital design techniques, however, it is questionable, how these techniques...
SRAM-Based FPGAs represent a low-cost alternative to ASIC device thanks to their high performance and design flexibility. In particular, for aerospace and avionics application fields, SRAM-based FPGAs are increasingly adopted for their configurability features making them a viable solution for long-time applications. However, these fields are characterized by a radiation environment that makes the...
Flash memories are gaining prominence for utilizing in large scale data centers (DCs) due to their high memory density, low power consumption and heat dissipation, and high access speed characteristics. The rate of degradation for a flash memory is largely affected by the amount and frequency of the erase/write operations, which is a challenge in the DC context that serves dynamically changing workloads...
The technology uses TCP / IP as the basic means of communication, adding a custom data communication protocol, through the integration of distributed storage scheduling ideas, multiple FPGA development board simulation into a large number of storage devices, through the unified mapping of the target data protocol Processing, to achieve data security, stable and reliable cloud storage, and because...
Recently, FPGA-based NCS applications have been widely used. Industrial environments have a lot of electromagnetic interference which may induce transient and permanent faults. As a result, Fault-Tolerant FPGA based NCS applications are required. In this paper, an NCS model composed of a combination of S2A architecture and In-Loop architecture connected to each other through Ethernet switch, is described...
Field Programmable Gate Array (FPGA) system is widely used in deep learning application and cloud system for acceleration. Quality and reliability of IP block is essential to the successful development of today's complex hardware acceleration design. In this paper, we discuss the important issues of quality and reliability of digital soft IP, and propose a qualification measurement system that can...
In this paper, we propose Joint Latch (JLatch) and Joint Flip-Flop (JFF), two novel reconfigurable structures which bring the reconfigurability of reliability to user latches and flip-flops (FFs) in reconfigurable devices such as FPGAs. Specifically, we implement two reconfigurable storage elements that exploit a trade-off between reliability and amount of available resources. In fault prone conditions,...
We present a digital implementation of a correlation receiver for pulsed CDMA lidar signals in direct-time-of-flight systems. A coded time-of-flight lidar is capable to identify its own signals and to reject state-of-the-art uncoded or differently coded pulses. The required sampling rate of the system ADC is determined. For processing the digitized receive signal a correlation filter realized in FPGA...
A novel true random number generator is proposed and implemented on XC6SLX16. It consumes 44 LUTs and generates output bitrate at 125 Mbps without post-processing, or 2000 Mbps with post-processing. The underlying mechanism of chaotic dynamics in Boolean chaotic oscillator is also researched. With the utilization of the proposed entropy source, the new scheme can precede referenced designs in reliability,...
Arbiter Physical unclonable function (A-PUF) with exponential number of challenges is an ideal candidate to realize lightweight and robust device authentication in Internet of Things applications. Unfortunately, it is particularly difficult to attain highly reliable responses and increase its modeling attack resistance simultaneously. This paper presents an approach to reduce the vulnerability of...
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