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As transistors decrease its size due to scaling, digital circuit capabilities increase. These increases are evident in terms of area, power, and speed. Due to the small nature of these devices, introducing parallel paths further increases functionality. Certain characteristics of FPGAs provide alternatives to achieve these improvements in a similar fashion. Partial reconfiguration(PR) further improves...
This paper evaluates the efficiency and performance impact of a dual-core lockstep as a method for fault-tolerance running on top of FreeRTOS applications. The method was implemented on a dual-core ARM Cortez-A9 processor embedded into the Zynq-7000 APSoC. Fault injection experiments show that the method can mitigate up to 63% on the FreeRTOS applications. This result is very near to the mitigation...
In this paper we focus on the issues of hardware implementation of genetic algorithms (GA) in hardware. In their classic implementation, the genetic algorithms search for a global minimum or maximum of a multidimensional function called the fitness function. If the problem, i.e. the fitness function, is too complex for a brute force search, we can look for a solution based on GA. In this situation...
In this paper, a low-cost accelerator for the ηT pairing in characteristic three over the super-singular elliptic curves is designed. As the critical operations of ηT pairing, the cubing and sparse multiplications over GF(36m) in the Miller's algorithm are merged and their arithmetic are modified and scheduled to reduce the intermediate data related overhead. With these optimizations, the Miller's...
Post Silicon Validation is critical step in order to deliver quality microcontroller chips to customers but is increasingly becoming complex and time consuming process as the design size is increasing. Due to increased number & diversity of design intellectual property, microcontroller post silicon validation has moved towards customized validation concept and hardware setup for individual design...
Traditional processor design approaches using CISC and RISC philosophies suffer from low performance. One of alternative approaches to improve system performance is instruction level parallelism (ILP). Among the processor architectures supporting ILP, very long instruction word (VLIW) processors offer some advantages such as low power consumption and hardware complexity. In this paper, we introduce...
This paper presents a Controller Area Network (CAN) communication system in the Field-Programmable Gate Array (FPGA), which is Xilinx Artix-7. Hardware circuits and the software flow char are described in detail. The reusable IP (Intellectual Property) technology is used in FPGA as the core controller. In addition, the CAN communication system is implemented by System-on-a-Programmable-Chip (SOPC)...
FPGAs are promising candidates for computational tasks in space. However, they are susceptible to radiation-induced errors in their configuration memory. The recovery of configuration errors, either by device scrubbing or by module-based recovery, involves a series of reads and writes to the FPGA's configuration port, and is efficiently performed on-chip by a fast, flexible and reliable reconfiguration...
In Systems Biology, Boolean models are gaining popularity in modeling and analysis of qualitative dynamics of gene regulatory mechanisms. With the development of advanced high-throughput technologies, the availability of experimental data on gene-gene, gene-protein interactions is ever increasing. Consequently, modern Boolean models are increasing in size and complexity. Software simulation of Boolean...
Heterogeneous computing with hardware accelerators is a promising direction to overcome the power and performance walls in traditional computing systems. CPU-accelerator integrated architectures, such as CPU with ASIC or FPGA based accelerators, are able to provide customized processing according to application requirements and are thus particularly attractive to speed up computation-intensive applications...
This, paper presents the FISH (FPGA-Initiated Software-Handled) framework which allows FPGA accelerators to make system calls to the Linux operating system in CPU-FPGA systems. A special FISH Linux kernel module running on the CPU provides a system call interface for FPGA accelerators, much like the ABI which exists for software programs. We provide a proof-of-concept implementation of this framework...
The Frisch-Waugh-Lovell (FWL) Recursive Least Squares (RLS) algorithm has been recently proposed as an RLS algorithm with lower computational cost and better numerical properties. We propose a VHDL implementation that has been successfully implemented on a Xilinx Virtex-7 FPGA. The FWL RLS algorithm has a complexity of L2 + O(L) products, instead of 1.5L2 O(L) as in conventional RLS algorithms. Because...
Toward integrating memristors in CMOS-based designs flexible prototyping environments are necessary. However, research in digital memristive systems so far lacks an adequate testing platform for real world devices. To achieve better handson experience, we developed a flexible FPGA-based solution which allows to link memristors with arbitrary compute units such as MIPS, ARM processor cores or own custom...
This paper presents a Field Programmable Gate Array (FPGA) based implementation of the Fourier Segmentation process that is used in the Empirical Wavelet Transform. The Empirical Wavelet Transform is a method to determine the modes of a given signal by building wavelets that are adapted to the processed signal. Such wavelets are constructed by determining the location of the information in the spectrum...
In fields like embedded vision, where algorithms are computationally expensive, hardware accelerators play a major role in high throughput applications. These accelerators could be implemented as hardwired IP cores or Application Specific Instruction-set Processors (ASIPs). While hardwired solutions often provide the best possible performance, they are less flexible then ASIP implementation. In this...
This article, describes the implementation of QPSK modulator and FPGA programming aspects for carrier frequency control for data transmission units in space applications. The module occupies lesser area for integration, operates on lower power and supports higher data rates than conventional modulator units of Indian Space Research Organization (ISRO). The scope of a miniature and low power modulator...
A 1 Volt, 8-bit, Successive Approximation Register Type ADC, with variable conversion time is implemented using FPGA SPARTAN-6 Board. The proposed ADC is design to achieve different number of conversion cycle for different sample values. Input signal as triangular wave with both positive and negative cycle is taken, But the DAC used in feedback is design to give analog output only for positive cycle...
Hardware implementations of Object-Tracking Algorithms, like most integrated circuits, are susceptible to radiation-induced soft errors. This work evaluated the reliability of a field-programmable gate array (FPGA) prototype for object-tracking algorithms via fault emulation experiments conducted at the register-transfer level (RTL). Faults were injected into the main sub-modules within the object-tracking...
Matrix inversion for real-time applications can be a challenge for the designers since its computational complexity is typically cubic. Parallelism has been widely exploited to reduce such complexity, however most traditional methods do not scale well with the matrix size leading to communication bottlenecks. In this paper we exploit a decentralised parallel hardware architecture based on a strongly...
Sophisticated embedded systems are increasingly used in defence, aerospace and avionic industries. They are responsible for control, collision avoidance, pilot assistance, target tracking, navigation and communications, amongst other functions. In this industrial field, High Performance Embedded Computing (HPEC) applications are becoming highly sophisticated and resource consuming for three reasons...
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