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While efficient simulators for Time-Multiplexing Cellular Neural Networks have been reported, no reports on implementations in FPGA have been presented. A Time-Multiplexing Cellular Neural Network is implemented within a FPGA for image processing. The network has been used to perform tasks, such as edge detection and noise remover over several test templates. Implementation results are compared with...
Research tools targeting commercial FPGAs have most commonly been based on the Xilinx Design Language (XDL). Vivado, however, does not support XDL, preventing similar tools from being created for next-generation devices. Instead, Vivado includes a Tcl interface that exposes Xilinx's internal design and device data structures. Considerable challenges still remain to users attempting to leverage this...
Pedestrian detection is a vital function of the emerging autonomous vehicle industry. HOG is widely used as the feature extractor for pedestrian detection thanks to its high accuracy despite the fact that it is computationally expensive. Hardware accelerators using GPUs or FPGAs are used in several proposals to address its real-time execution. There is always a trade-off between real-time processing,...
In this paper, we describe a Selectable Grained Reconfigurable Architecture (SGRA) in which each Configurable Logic Block can be configured to operate in either fine-grained or coarse-grained mode. Compared with the Mixed Grained Reconfigurable Architecture (MGRA), which has a fixed ratio of fine- and coarse-grained operation blocks and a heterogeneous floorplan, SGRA offers greater flexibility in...
This article shares experience and lessons learned in teaching course on programmable logic design at Universitas Muhammadiyah Surakarta, Indonesia. This course is part of bachelor of engineering (electrical) degree program. Project-based approach is chosen to strengthen these students' understanding and practical skills. Each year's project involves challenges for the students to solve by implementing...
This paper reports heavy ion induced single event effects (SEE) results for a variety of microelectronic devices targeted for possible use in JPL spacecraft. The compendium covers devices tested within the timeframe of August 2015 through July 2017. It is formatted as an update to the SEE compendia JPL has historically published.
Coarse-grained reconfigurable arrays (CGRAs) are a style of programmable logic device situated between FPGAs and custom ASICs on the spectrum of programmability, performance, power and cost. CGRAs have been proposed by both academia and industry; however, prior works have been mainly self-contained without broad architectural exploration and comparisons with competing CGRAs. We present CGRA-ME - a...
As we have seen in this paper, FPGAs are a good candidate for implementing compute-intensive algorithms. Although the processing frequency is more than 10 times lower, their capability to process multiple data channels in parallel compensates for it and gives them an advantage in relation to CPUs. By comparing the results we see that the processing time was sped up by factor of 3 with 60% of the resources...
In this paper are presented the implementation of some blocks of software radar receiver on the PXI platform. Realization of the processing of radar signals in real time is achieved. Comparative analysis of the results of detection of real radar targets between the offline and processing in real time on the appropriate hardware components is shown.
In recent years, the information technology world have faced broad security issues due to the large amount of data flowing over the network. HW security solutions are often preferred in contexts where an high level of performance is required. Multiple HW implementation of the Advanced Encryption Standard can be found in literature. Although several optimization methods based on optimum composite field...
The combination of Battery-Ultracapacitor, as a Hybrid Energy Storage System (HESS) controlled with a bidirectional buck-boost converter for light electric vehicles is presented in this paper. By combining these two energy storage elements an efficient supply system can be obtained. A bidirectional Buck-Boost converter is used to control the energy transfer between the elements of the HESS and the...
In this paper we present a novel approach based on FPGA for the protection of power system based technology from under/over voltage. It has been always a matter of challenge to design the system with optimal power usage and protection from excessive voltage. Considering Power system, it has become very much necessary to have an additional system which is smart and capable of having intelligence to...
Reliability evaluation of Commercial off-the-shelf (COTS) processors against faults induced by radiation is a challenging problem. Some alternatives have been proposed to radiation test but they are very time consuming and lack of the observability needed. This work analyses the possibility to use an HDL model for estimating applications dependability on Texas Instruments MSP430 processor early in...
This paper introduces a new FPGA architecture optimized for Frequency Modulated Continuous Wave (FMCW) Synthetic Aperture Radar (SAR). The architecture implements a Global-Backprojection-Algorithm (GBP) which has been modified to be independent of platform velocity (start-stop-approximation). The design supports parallelism of dedicated GBP processing modules in order to provide high performance....
This paper presents the design of RISC architecture based multicore processor using the Xilinx® development platform for designing and Spartan-6 FPGA for the implementation of the architecture. The light weight multithreaded kernel module is implemented on the top of the architecture to demonstrate the parallel programming potentials on the same. A task assigned to the processor is managed by the...
Complex computing platforms involving pipelined processors, memory hierarchies, multi-core and many-core architectures are very common nowadays. These approaches require a deep understanding of the underlying hardware and the corresponding programing model to be able to decide which alternative is more suitable, i.e. obtain the best performance at the minimum cost, for a given application. Hence,...
Microprocessor system is a must know subject in electrical engineering. Despite of learning through simulation, student, especially in polytechnic, have to be more involved in the hands on practice. Z80 is one of the simplest microprocessor system for studied. Many of existing Z80 learning board came with tons of user friendly interfaces, such as a keypad and alphanumerical LCD, however, the most...
Most modern FPGAs have very optimised carry logic for efficient implementations of ripple carry adders (RCA). Some FPGAs also have a six input look up table (LUT) per cell, whereof two inputs are used during normal addition. In this paper we present an architecture that compresses the carry chain length to N/2 in recent Xilinx FPGA, by utilising the LUTs better. This carry compression was implemented...
This paper presents the design and implementation of a 64-bit VLIW microprocessor. It discusses the concept, traits, principle and structure of this 64-bit VLIW microprocessor to facilitate its design. This paper first discusses the architectural specifications of the microprocessor and the 16 kinds of operational functions it facilitates. It then examines the implementation of the whole VLIW microprocessor...
This paper design an embedded controller module based on ARM according to the VME bus specification to meet the increase of VME controller performance, interface optimization and the increasing demand of hardware and software compatibility. Hardware-wise, we design the peripheral circuit for ATSAMA5D3 microprocessor, achieve a network port, USB port and other external interfaces, and use the FPGA...
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