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The following topics are dealt with: neurosynaptic integrated circuit; digital microfluidic biochips; supercomputer; flip-flops; ARM-FPGA; CPU; system-on-chips; vehicle intelligence; convolutional neural networks; silicon-on-insulator; STT-RAM; video signal processing; and CMOS integrated circuit.
Optical interconnection is a potential substitute for electrical interconnection in the chip integration field, as it can ultimately solve the problems such as crosstalk and electric migration brought by electrical wires. In the paper, a short frame asynchronous optical communication protocol is proposed to implement the inter-chip optical communication between the microprocessor and the static memory...
Demand is increasing daily for a robust VLSI chip that is useful for operating under a radiation-rich space environment, such as spacecraft, space satellites, and space stations. Optically reconfigurable gate arrays (ORGAs) have been developed to realize a large virtual gate count that is much larger than those of current VLSI chips by exploiting the large storage capacity of a holographic memory...
Stencil computation is one of the important kernels in scientific computations, however, the sustained performance is limited by memory bandwidth especially on multi-core microprocessors and GPGPUs due to its small operationalintensity. In this paper, we propose a scalable streaming-array (SSA) of simple soft-processors for high-performance stencil computation on multiple FPGAs. The SSA architecture...
A design plan of digital video broadcasting-cable is introduced in this dissertation. The design is based on Xilinx Spartan-6, which has high performance and low power expended, and AD9789, a DVB used chip designed by ADI. The architecture and function of AD9789 is introduced, including the whole design of the system and the realization of variable symbol rate.
We demonstrate a hardware implementation of a complex event processor, built on top of field-programmable gate arrays (FPGAs). Compared to CPU-based commodity systems, our solution shows distinctive advantages for stream monitoring tasks, e.g., wire-speed processing and predictable performance. The demonstration is based on a query-to-hardware compiler for complex event patterns that we presented...
The paper presents design and implementation of a wireless sensor node suitable for medical applications. As physiological signals are highly redundant, the data compression algorithms (Huffman's coding) are used to save energy and improve the node performance. Design is based on the ARM Cortex M1 processor and implemented in FPGA.
This paper describes a micro-architecture for a custom programmable FPGA-based processor, with direct support for streaming and vector computations relying on custom cache memory storage. The processor combines a custom data-path with several parallel data ports for accessing operands in streaming mode thus efficiently supporting nested looping constructs found in high-level languages while mitigating...
Multi-core system is becoming the next generation embedded design platform. Heterogeneous and homogeneous processor cores integrated in Multiple Instruction Multiple Data (MIMD) System-on-a-Chip (SoC) to provide complex services, e.g. smart phones, is coming up in the horizon. However, distributed programming is a difficult problem in such systems. Today, only in very few MIMD SoC designs we can find...
This paper presents a reliable processor pipeline architecture resilient to multiple soft- and timing errors. It also presents a probabilistic quantification of its performance overheads. This reliable processor pipeline architecture has been implemented in the Leon3 VHDL open source processor. An FPGA prototype running under random fault injection has also been developed. This reliable processor...
As communication networks move towards 40/100G transmission capacities, wire-speed packet processing is becoming much critical to implement. Most commercial solutions for the high-speed telecom market are based on either ASIC designs and/or network processors (NPs), while enterprise solutions can eventually make use of general purpose processors (GPPs) to deal with much slower processing requirements...
The need of critical applications has derived in the development of several safety techniques that aim to guarantee system operability. The vast majority of these systems own a microprocessor to control its functionality. Thus, system reliability largely depends on the proper function of the microprocessor. In the special case of SRAM FPGAs, Triple Modular Redundancy (TMR) combined with Dynamic Partial...
To improve the speed of the image processing chip, to quick share the market and to reduce costs, this paper designs a chip with Harvard Architecture and FPGA. The chip is also used with a new hardware algorithm. Using the chip, the processing time is 13.2% less than the time of the chip with Von Neumann Architecture. The used units of filter are 13% of the whole FPGA gates, less than the claim part...
Neuromorphic systems have been increasing in size and complexity in recent years, thanks also the adoption of the Address-Event Representation (AER) as a standard for transmitting signals among chips, and building multi-chip event-based systems. AER mapper devices that route Address-Events from multiple sources to different multiple destinations are crucial components of these systems, as they allow...
This paper describes a self-configurable middleware and a node execution platform to support autonomous sensor networks. We achieve self-configuration by scheduling and strategies similar to load balancing (mapping) that is integrated in our proposed middleware. On the node execution platform we decide on the fly between microprocessor and FPGA realization of hybrid tasks. We propose a combination...
This is a design of a stable and reliable control and drive system of IGBT, according to the requirement of the dynamic harmonic filter. This design is centrally controlled by a 89C52 MCU and it mainly consists of 89C52 MCU, FPGA, touch screen, alarm circuit, drive and protection circuit, intelligent electrical energy sensor. It has main functions of collection of harmonic parameters of the power...
In this paper, we present an architecture and corresponding analysis for large-scale neuromorphic systems using a digital approach where neurons are abstracted as arithmetic logic units and communication processors. After presenting the architecture, we establish a few basic architectural principles, particularly the scaling of the system to large arrays. We demonstrate the reality of a single chip...
Nowadays, computers are indispensable tools for most of everyday activities ranging from consumer electronics to industrial process automation. Complexity of new applications leads computer engineers to use embedded systems in order to develop high performance technological solutions that can achieve high speed processing while exploiting hardware resources efficiently. In order to develop embedded...
We present a hardware-accelerated implementation of a bottom-up visual attention algorithm. This algorithm generates a multi-scale saliency map from differences in image intensity, color, presence of edges and presence of motion. The visual attention algorithm is computed on a custom-designed FPGA-based dataflow computer for general-purpose state-of-the-art vision algorithms. The vision algorithm...
Integrated Modular Avionics (IMA) architecture provides means for integrating multiple safety-critical applications on a shared hardware in an airborne system. Error free data transfer between different modules of an IMA cabinet is an issue of critical importance. ARINC 659 has proven to be one of the most comprehensive standards for intra-cabinet data transfer within an IMA cabinet of commercial...
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