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A three-dimensional vehicle routing problem for urban last-mile logistics (3-DVRP for ULML) is formulated, toinclude the vertical dimension, aim to account for verticaldistances in a high-rise urban environment. The crux of theproposed objective function lies in addressing a research gap to account for the vertical distance and minimizing the total node-to-node (N2N) travel and service time which...
Energy minimization is of great importance in wireless sensor networks in extending the battery lifetime. One of the key activities of nodes in a WSN is communication and the routing of their data to a centralized base-station or sink. Routing using the shortest path to the sink is not the best solution since it will cause nodes along this path to fail prematurely. We propose a cross-layer energy...
Underwater networks that are designed to carry high-priority data at a relatively high traffic load should employ network protocols that emphasize low delay and adequate reliability at the expense of energy. ICRP (Information-Carrying based Routing Protocol), originally proposed by Wei Liang et al. [1] in 2007, is a routing protocol that obtain unicast routing paths by sending data payload as broadcast...
The analysis of network routing games typically assumes, right at the onset, precise and detailed information about the latency functions. Such information may, however, be unavailable or difficult to obtain. Moreover, one is often primarily interested in enforcing a desirable target flow as the equilibrium by suitably influencing player behavior in the routing game. We ask whether one can achieve...
In this paper we propose a fuzzy based routing algorithm in which the link cost are dynamically assigned using a fuzzy system. Based on a set of fuzzy rules, link cost is dynamically assigned depending upon the current condition of the network. The proposed fuzzy scheme determines the integrity of a link given the current congestion state calculated via the delay experienced in the network and the...
This paper explores the performance and optimization of the IBM Blue Gene/Q (BG/Q) five dimensional torus network on up to 16K nodes. The BG/Q hardware supports multiple dynamic routing algorithms and different traffic patterns may require different algorithms to achieve best performance. Between 85% to 95% of peak network performance is achieved for all-to-all traffic, while over 85% of peak is obtained...
In this paper, we propose a novel approach based on particle swarm optimization (PSO) for solving the minimum energy broadcast (MEB) problem, which has been proven to be NP-complete. Wireless sensor networks (WSNs) have attracted large intention in recent years due to its powerful ability. One crucial issue in WSN is energy saving because of the limited battery resource. The MEB problem is one of...
OSPF (Open Shortest Path First) and EIGRP (Enhanced Interior Gateway Protocol) are routing protocol which is a member of IGP (Interior Gateway Protocol). OSPF and EIGRP will distribute routing information between routers in the same autonomous system. This research will find how routing protocol works and compare those dynamic routing protocols in IPv4 and IPv6 network. This research will simulate...
The regularity of resources found in FPGAs is a unique feature, which can be utilized in a number of applications, e.g., in timing critical applications or applications with a demand for homogeneous routing. Current synthesis tools do not support an automatic generation of homogeneous FPGA designs, such that a time-consuming hand-crafted design is required. We present a tool flow, which automatically...
We present HORNET, a parallel, highly configurable, cycle-level multicore simulator based on an ingress-queued worm-hole router NoC architecture. The parallel simulation engine offers cycle-accurate as well as periodic synchronization; while preserving functional accuracy, this permits tradeoffs between perfect timing accuracy and high speed with very good accuracy. When run on 6 separate physical...
Thermal issue is one of the major challenges in the research field of three-dimensional (3D) IC. Network-on-Chip (NoC) has been viewed as a practical communication infrastructure in 3D IC. In this paper, we proposed an adaptive routing algorithm, Traffic- and Throttling-Awareness Routing (TTAR), to address the traffic congestion due to throttling of transient-temperature control. TTAR can balance...
The Wave Dynamic Differential Logic (WDDL) is considered as a relevant hardware countermeasure to increase the robustness of cryptographic devices against Differential Power Attacks (DPA). However, to guarantee its effectiveness, the routing in both the direct and complementary paths must be balanced, to obtain equal propagation delays and power consumption on differential signals.
Network routing is the mechanism chosen to send packets from any source to a destination in the network. The goal of any routing algorithm is to find an efficient path to send a packet to any destination taking into account all the obstacles that may be taking place in the network at any time. The focus of this paper is to provide an efficient solution to the routing problem by making use of reinforcement...
In order to improve the negative effect of increasing transformation cost of pseudo-Boolean Satisfiability algorithm in the routing process, a new routing algorithm was proposed for FPGA, which combined advantages of pseudo-Boolean Satisfiability and geometric routing algorithm. In the routing process, one of geometric routing algorithm-PathFinder was chosen firstly for FPGA routing. If not successful,...
Traditional physical design of FPGAs is usually divided into 2 phases, placement and routing. While it simplifies design modelling and algorithm implementation, some problems such as mismatches between the two will also occur when a valid placed circuit can't be globally routed. The mismatches can significant increase the overall runtime of the physical design. A new placement and global routing integrated...
The Network-on-Chip has been recognized as a paradigm to solve System-on-Chip (SoC) design challenges. The routing algorithm is one of key researches of a NoC design. Its importance and effect on the performance of the network is accordingly cardinal. High-performance, load-balance, deadlock-free and livelock-free, fault-tolerant are the desirable properties of a routing algorithm for NoC. In this...
State-of-the-art supercomputers consist of a huge number of computing nodes that are connected by an interconnection network. Although such large-scale systems have regular organizations, scaling study on the network is not sufficient so far. This paper focuses on two-dimensional torus network with two typical routing algorithms, i.e., dimension-order and Duato's protocol, and presents steady and...
We present a modified Built-In Self-Test (BIST) approach for programmable clock buffers in Xilinx Virtex-4, Virtex-5, and Virtex-6 Field Programmable Gate Arrays (FPGAs). While seemingly trivial, these critical clock buffer modules present interesting testing challenges as will be described in this paper. A timing problem was found in the previously reported BIST approach for the clock buffers, where...
As chip design complexity scales, completing routes of all nets has become a tough work under limited routing resources and increasing number of design rules. Besides, wirelength and crosstalk greatly affect the chip's performance. This paper presents a novel fine-grain track routing approach to optimize routability and crosstalk. The proposed track router is performed in a GRC-by-GRC fine-grain manner,...
This paper presents an efficient algorithm to detect the global topological similarity between two circuits. By applying the proposed circuit similarity algorithm in an incremental design flow, IDUCS (incremental design using circuit similarity), the design and optimization effort in the previous design iterations is automatically captured and can be used to guide the next design iteration. IDUCS...
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